User`s manual

Bit 1: RXSRC --- Receive FIFO DMA Source: This

bit determines which SCC pins are used to control transmit and receive

DMA transactions between the SCC and the internal FIFOs (when

enabled). The transmit data FIFO is always used with SCC channel A.

The receive data FIFO may be used with SCC channel A by setting RXSRC

to logic 0, or with SCC channel B by setting RXSRC to logic 1. (See page

29 for information on using channel B.)

W/REQADTR/REQA

Transmit

DMA

W/REQBW/REQA

Receive

DMA

RXSRC = 1

RXSRC = 0

Bit 0: Reserved, always 0.

Quatech MPAC-100 User's Manual