User`s manual

If Card and Socket Services has set the SIGCHG bit in the PCI Configuration
Status Register to a logic 1, the RING signal is routed to the STSCHG line on the PCI
bus. The signal is inverted by the RS-232 receiver, so a positive voltage on pin 22 will
assert STSCHG.
Table 17 shows the pin configuration of the MPAC-100 DTE connector. The
definitions of the interchange circuits according to the RS-232-D standard can be found
starting on page 52.
* Not included in the official RS-232-D specification
Comm. Reg. bit 7TMTEST MODEX25
TRxCA pin
DA
TXCLK
(DTE)
X
24
N/C
23
PCI STSCHG signalCERINGX22
Comm. Reg. bit 4
RL
RLBK
X
21
DTR/REQ
A pin
CD
DTR
X
20
N/C19
Comm. Reg. bit 5
LL
LLBK
X
18
RTxCA pin
DD
RXCLK
(DCE)
X
17
N/C16
TRxCA pin
DB
TXCLK
(DCE)
X
15
N/C
14
N/C13
N/C
12
RTxCA or TRxCB pin
*
RXCLK
(DTE)
X
11
SYNCA pin*SYNCAX10
N/C
9
DCDA pin
CF
CD
X
8
ABDGND7
DCDB pin
CC
DSR
X
6
CTSA pin
CB
CTS
X
5
RTSA pinCARTSX4
RxDA pin
BB
RXD
X
3
TxDA pin
BA
TXD
X
2
CGND1
SCC Pin or Register Bit
RS-232-D
Circuit
Signal
From
DTE
To
DTE
Pin
Table 17 --- Connector Pin Definitions
Quatech MPAC-100 User's Manual
48