Specifications

EPC-8A Hardware Reference
2
NE2000+ Ethernet controllers. Interface configuration (Emulation mode and address/
interrupt control) is software controlled; a DOS-based application is provided to
perform this operation.
• Second modified RS-422/485 PC-compatible serial port interface implemented with
RS-422/485 transmit and receive buffers. CTS, RTS, DSR and DTR are buffered to
RS-422 levels. The Transmit lines are controlled by the RTS signal, providing RS-485
multidrop support.
• Watchdog timer that you can configure to generate a VMEbus SYSFAIL signal and
reset the processor. The processor can be configured to reboot or halt. The timer is
implemented as a software-retriggerable one-shot, with a programmable reset interval
ranging from 125 mS to 8000 mS.
• The ability to boot from VMEbus memory or resident Flash memory.
• (Optional) 128 Kbytes of battery-backed memory-mapped static RAM.
• (Optional) 2 Mbytes of flash-EPROM based non-volatile memory. This memory can
be protected against accidental overwriting by removing a shorting jumper. Software
is available to support this in the DOS/Windows environment. This memory can also
be configured as a bootable disk.
VMEbus
The VMEbus implementation provides a complete bus interface with enhancements for
multiprocessor environments. For detailed information, continue reading.
System controller functions
With a single hardware configuration jumper, the EPC-8A can provide full VME SLOT-1
arbitration functions. When enabled, the provided functions include priority and
round-robin bus arbitration, IACK and bus grant daisy-chain driving, SYSRESET and
SYSCLK generation, and bus time-out detection. ROR (release-on-request) or a
fair-requester, RONR (release-on-no-request) bus release mechanism is software
selectable.
VMEbus master interface
The VMEbus master interface provides a full 32-bit data path to the 16, 24, and 32-bit
address spaces of the VMEbus. The bus interface is designed with a minimum number of
state registers, which maximizes performance in a multitasking or interrupt-driven
environment.
Programmable hardware byte-swapping is provided for ease of communication with other
processor architectures that may share the VMEbus. All the VMEbus address spaces can
be addressed from both protected-mode and real-mode operating systems.
The EPC-8A can generate or respond to all 7 standard VMEbus interrupts, and can also
receive the VMEbus signals ACFail, BERR, and Sysfail as interrupts. When it is used to
generate interrupts, it implements 16-bit IACK cycles.