Specifications

EPC-8A Hardware Reference

WDT (bit 3 of register 8154h) is set. A local “warm” hardware reset occurs. Bits 1, 2, and

3 of register 815Dh are cleared to prevent the watchdog timer from expiring on a warm

reset that is initiated from a source other than a watchdog timeout. The BIOS must set the

BTOE bit. VME SYSFAIL* is also asserted. When exiting a hardware reset condition, the

BIOS can check the WDT bit. If this bit is set (0), then a watchdog timeout caused the

hardware reset (as opposed to SYSRESET or power-on reset). Then depending on the

value of a setup option the BIOS either HALTs the CPU or allows the boot process to

continue. At this point, software may deassert the VME SYSFAIL* condition by reading

the register at 815Dh.

Note that a watchdog hardware reset results in are “warm” hardware reset. A warm

hardware reset clears all register bits except for the upper four bits of the Configuration

Control registers (these control bus timeout function and watchdog timer functions). A

warm reset does clear WDTR (bit 3 of the Module Status/Control register) to allow the

hardware to be released from the warm reset state, but SYSFAIL continues to be driven

until the WDT bit is cleared by either reading the Module Status/Control Register or by a

power-on reset.

If WDTR is clear, WDT mask (bit 3 of register 8155h) enables an interrupt if a timeout

event occurs (SYSFAIL is not driven). The clock is disabled to the counter if the interrupt

is pending and not serviced. Service of the interrupt is signaled to the counter by reading

signaled on IRQ10. The timer event also clears WDT bit in the BES register (bit 3 of

Application software that utilizes this timer should take care to reset the counter just prior

to enabling the interrupt bit in register 8155h. This inhibits a spurious timer event from

occurring just after enabling the timer.

Battery

The battery powers the CMOS RAM and TOD clock when system power is not present.

At 60ºC, the battery should have a shelf life of over four years. In a system that is powered

on much of the time and where the ambient power-off temperature is less than 60ºC, the

battery is estimated to have a life of 10 years.

If system power is present, the VME +5V STDBY voltage also powers the CMOS RAM

and TOD clock. This is done with isolation diodes, so that either the onboard battery or the

VME voltage supplies power. Neither power source affects the other.

The 3.0V lithium battery supplied with the EPC-8A is a Panasonic BR2330 “coin cell” or

equivalent. It is mounted behind the reset button at the top of the EPC-8A. Should the

battery fail, you may obtain and install a replacement.

Replacing the battery is a simple task. However, removing the battery invalidates the

CMOS setup parameters if you do not put the new battery into the empty socket within

about 60 seconds. It is recommended that all setup parameters be written down while the

battery is still good, or saved using the CMOS Save and Restore feature. For a method to

backup CMOS parameters into a Flash memory feature block, see the description of the

CMOS Backup and Restore feature on page 32.

To replace the battery, lay the EPC-8A flat on an ESD-protected surface. Remove the

SIMM module, following proper ESD protection procedures. Now slide the battery out