Specifications

EPC-8A Hardware Reference
36
TEST This LED is lit whenever the system is running its power-on self-test, as
reflected in the PASS bit in the VXI registers. If PASS is 0, then this LED is
lit. This only occurs during a hardware reset.
Resetting the EPC-8A
You can reset (reboot) the EPC-8A in a number of ways. Resets are summarized in the
table below, with details in the paragraphs that follow.
Power-off, Power-on
Known as a cold hardware reset. This causes all boards in the VMEbus to reset. The
system runs the power-on self-test and reboots the OS.
Power low
“Warm” hardware reset. When power is detected between ~3.0 and ~4.5V, the system runs
the Power On Self Test (POST) and reboots the operating system. When power is less than
~3.0V, the system performs a cold hardware reset.
Front-panel Reset button
“Warm” hardware reset. The Reset button causes the EPC-8A to perform a hardware reset.
The system runs the power-on self-tests and reboots the operating system.
Table 4-3. Reset Conditions
Power-On
Reset
Power < 3.0 V Power 3–4.5 V
Front-Panel
Reset Button
Ctrl-Alt-Del
VMEbus SYSRESET
Asserted
Watchdog
Timer
“Cold” reset “Cold” reset “Warm” reset “Warm” reset Software
reset
“Warm” reset “Warm” reset
POST runs POST runs POST runs POST runs No POST POST runs POST runs
R400EX, all
VXI registers
reset
R400EX, all
VXI registers
reset
R400EX, most
VXI registers
reset
R400EX, most
VXI registers
reset
R400EX, most VXI
registers reset
R400EX,
most VXI
registers reset
bits 4
–7 of
8102h not reset;
bits1,2,4 & 6 of
815Dh not reset
bits 4–7 of
8102h not reset;
bits1,2,4 & 6 of
815Dh not
reset
bits 4
–7 of 8102h
not reset; bits 1, 2,
4 & 6 of 815Dh not
reset
bits 4–7 of
8102h not
reset; bits 1, 2,
4 & 6 of 815Dh
not reset
AT. RESET
generated
AT. RESET
generated
AT. RESET
generated
AT. RESET
generated
No AT.
RESET
AT. RESET
generated
AT. RESET
generated
SYSRESET*
generated
SYSRESET*
generated
SYSRESET*
not generated
unless bit 6 of
815Dh is set
SYSRESET*
not generated
unless bit 6 of
815Dh is set
No
SYSRESET*
SYSRESET* not
generated unless
bit 6 of 815Dh is set
SYSRESET*
generated
SYSFAIL
asserted until
watchdog
timer is reset