Specifications

Chapter 4: Theory of Operation

Ctrl+Alt+Del

“Warm” software reset. This keyboard sequence is also called a “warm boot”. The

EPC-8A does not reinitialize all of the processor’s hardware. The power-on self-test does

not run. However, the operating system is reloaded.

VMEbus SYSRESET

“Warm” hardware reset. The EPC-8A can be software-configured to respond or not

respond to the VMEbus SYSRESET* line. Asserting bit 7(SRIE) of register 8144h allows

the VME SYSRESET* signal to reset the EPC-8A. The reset semantics are the same as

the front panel reset.

Watchdog Timer

“Warm” hardware reset. Same as a front panel reset button except that SYSFAIL is

asserted until the watchdog timer is cleared.

A “cold” or hardware reset of the EPC-8A (not a keyboard Ctrl+Alt+Del reset) clears all

of the register bits to 0, except for RELM, ARBM, and ARBPRI, which may be in an

undefined state. (All bits, however, are cleared by a power-on reset.) However, this may

not be apparent because the BIOS initialization sequence then reinitializes values in these

the setup screen.

VME/VXI Soft RESET state and SYSRESET

“Soft Reset” is a capability that allows another VME master to disable the EPC-8A’s

connection to the VME bus, without interrupting (or resetting) the 486 processor on the

EPC-8A.

The Soft Reset state is entered when the SRST bit is set. In this state the EPC-8A removes

any asserted interrupts (clears the Interrupt Generator register, disables its VME master

logic, asserts both the VMER and BERR sticky bits in the VME Event State register,

disables watchdog timer resets and interrupts, and clears the PASS bit SYSFAIL is also

asserted if the NOSF (SYSFAIL inhibit) bit is clear. The Slot-1 arbitration and control

logic and the bus timeout function, if it is enabled, is unaffected by the SRST bit. Software

on the EPC-8A can detect that another board has set the EPC-8A into Soft Reset state by

several different methods:

1. Enable the interrupt events associated with either the VMER bit or BERR bit.

2. After each VME master access poll the BERR bit. If this bit is set either a true bus

timeout occurred (VMER is not asserted in this case) or the Soft Reset state has been

entered (both VMER and the BERR bits are asserted).

The Soft Reset state can be exited by a push-button reset, a power-on reset, by simply

writing a 0 to the SRST bit, or by the assertion of SYSRESET when the SRIE bit is also

set. When SRST is cleared by writing the bit to 0, the VMER and BERR bits should also

be cleared by writing to the VME Event State register, VME master accesses are again

enabled (if they were enabled prior to SRST being asserted), and the watchdog functions,