Specifications

EPC-8A Hardware Reference
40
Byte Ordering
There are two fundamentally different ways of storing numerical values in byte locations
in memory:
• Little endian, characteristic of Intel microprocessors, where the least-significant data
byte (LSB) is stored in the lowest byte address
• Big endian, characteristic of Motorola microprocessors and the VMEbus environment
in general, where the most-significant data byte (MSB) is stored in the lowest byte
address
The EPC-8A contains programmable byte-swapping hardware to allow programs to read
or write VMEbus memory in either byte order. When using the E-page to access the
VMEbus, the order is selected by bit 5 (BORD) in the VME modifier register (8151h)
When using direct memory mapping, the order is address-range dependent (For example,
E0000000–E0FFFFFF accesses the A24 space with big endian byte ordering, and
20000000–20FFFFFF accesses the A24 space with little endian byte ordering).
When performing a single byte (D08) access, the byte order makes no difference.
However, word (D16) or double-word (D32) accesses may require byte-swapping.
When little-endian is selected, bytes pass straight through unchanged. Little endian should
only be used when reading or writing data between two Intel processor systems. The
results of using little-endian byte ordering to transfer a double-word integer between an
Intel processor and a Motorola processor are shown below.
Since the 486 processor uses Addr as the least-significant byte and the Motorola processor
uses Addr as the most-significant byte, the processor receiving the data gets a “scrambled”
value.
Address + 3 Address + 2 Address + 1 Address
Byte 3Byte 2Byte 1Byte 0
MSB LSB
Address + 3 Address + 2 Address + 1 Address
Byte 3Byte 2Byte 1Byte 0
LSB MSB
Figure 4-3. Using little-endian byte ordering
76 54
32 10 = 76543210h
486
Address
Addr+3 Addr+2
Addr+1
Addr
76 54
32 10 = 10325476h
Motorola
Address
Addr+3 Addr+2 Addr+1 Addr
LSB
MSB