Specifications

Chapter 5

Programming the

VMEbus Interface

This chapter describes the EPC-8A VMEbus interface as seen by a program. Users should

avoid direct use of most of these facilities. Whenever possible, the VMEbus interface

should be accessed through the EPConnect software or other higher level programming

facilities.

The EPC-8A VMEbus interface registers are defined in Appendix F, Registers. For

specific bit definitions, refer to that appendix.

Concepts

The VMEbus interface on the EPC-8A is primarily for master accesses out onto the

VMEbus. The only exceptions to this are the VXI-defined registers accessible in the A16

space discussed in the previous chapter. There is no slave memory accessible in the A32 or

A24 address spaces.

VMEbus accesses are performed in either of two ways. For real-mode operating systems,

a 64Kbyte “window” is provided in high memory accessed at 0E0000–0EFFFF. Any

64Kbyte region of the VMEbus (all address spaces) can be mapped behind this “E page”

window such that the VMEbus address space is visible to the operating system memory

map. For protected mode operating systems, the EPC-8A provides direct mapping of the

VMEbus into the PC memory space above 256 MByte.

Atomic access

The EPC-8A supports atomic access to the VMEbus data for data lengths not greater than

32 bits and only then if it is aligned to its natural boundary; for instance, 32-bit data must

be aligned on a 32-bit address.

Read-Modify-Write Operations

VMEbus RMW (read-modify-write) cycles can be performed through use of the LOCK

instruction prefix with certain instructions. All of these instructions perform a read

followed by a write. When such a read occurs that is mapped to the VMEbus, the EPC-8A

treats it as the start of a VME RMW cycle. The next VME access from the CPU is treated

as the write that terminates the RMW cycle. Keep in mind that accesses that cross a 32-bit

boundary are actually performed as two accesses. For this reason, RMW accesses that

cross a 32-bit boundary do not behave as expected. Also, many compilers do not actually

generate a 32-bit access. Instead, two 16-bit accesses are generated. This can also cause an

32-bit RMW cycle to terminate prematurely with unexpected results.