Specifications

EPC-8A Hardware Reference
vi
Resident Flash/SRAM Memory ................................................................................................................ 33
Resident Flash Memory...................................................................................................................... 33
SRAM................................................................................................................................................. 33
Watchdog Timer........................................................................................................................................ 33
Battery........................................................................................................................................................ 34
Peripheral Ports.......................................................................................................................................... 35
RS-232 Port........................................................................................................................................ 35
RS-422/485 Port................................................................................................................................. 35
Parallel Port ........................................................................................................................................ 35
Keyboard ............................................................................................................................................ 35
Front Panel LEDs ...................................................................................................................................... 35
Resetting the EPC-8A................................................................................................................................ 36
Power-off, Power-on .......................................................................................................................... 36
Power low........................................................................................................................................... 36
Front-panel Reset button .................................................................................................................... 36
Ctrl+Alt+Del ...................................................................................................................................... 37
VMEbus SYSRESET......................................................................................................................... 37
Watchdog Timer................................................................................................................................. 37
Register State after Reset........................................................................................................................... 37
VME/VXI Soft RESET state and SYSRESET.......................................................................................... 37
Signal Register FIFO ........................................................................................................................................ 38
EXM Expansion Interface ................................................................................................................................ 38
VME Interface .................................................................................................................................................. 39
Connectivity............................................................................................................................................... 39
VMEbus System (Slot-1) Controller Functions ........................................................................................ 39
VMEbus Access......................................................................................................................................... 39
Byte Ordering ............................................................................................................................................ 40
VMEbus Interrupt Response...................................................................................................................... 41
VME Extension Registers (VXI)............................................................................................................... 41
Passing VME Interrupts and Events to the CPU .............................................................................................. 42
Chapter 5: Programming the VMEbus Interface
Concepts............................................................................................................................................................ 43
Atomic access............................................................................................................................................ 43
Read-Modify-Write Operations................................................................................................................. 43
Setting the VMEbus Access Bit........................................................................................................................ 44
Real-Mode “E-page” VMEbus Accesses.......................................................................................................... 44
Supported Address Modifiers ........................................................................................................................... 45
Low-Level Programming “E” Page Accesses .................................................................................................. 45
Example #1................................................................................................................................................ 45
Example #2................................................................................................................................................ 46
Low-Level Handling of VMEbus Interrupts ............................................................................................. 47
Start of Loop....................................................................................................................................... 48
Protected-Mode Direct VMEbus Accesses....................................................................................................... 48
Generating IACKs in Protected Mode.............................................................................................................. 49
Programming the Watchdog Timer .................................................................................................................. 50
Appendix A: Chipset and I/O Map................................................................................................................. 51
Appendix B: Interrupts and DMA Channels
Interrupts........................................................................................................................................................... 57
DMA Channels ................................................................................................................................................. 57