Specifications

EPC-8A Hardware Reference
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high-order address nibble is 1, C, or D, i.e., only in A16 direct access mode). Note that an
IACK overrides any of the other access modes.
With the EPC-8A programmers are not restricted to using the E-page to signal an IACK;
direct VME memory access is possible. In protected mode you cannot access physical
addresses—only virtual addresses. Thus for addressing, map the flat 32-bit physical
address to a virtual pointer.
To acknowledge a VME interrupt and acquire its 16-bit status/ID:
1. Multiply the VME interrupt number by two and add the result to 0xC4000000.
2. Map the resulting physical address 0xC4000000 to a protected mode address.
3. Read the 16-bit status/ID value from the resulting virtual mode address.
Whether or not a protected mode environment uses virtual memory is an attribute of the
operating system, not of being in protected mode. There are protected mode environments
that do not use virtual memory (like most DOS extenders).
Programming the Watchdog Timer
The watchdog timer on the EPC-8A can be set to either halt the system or reboot when a
watchdog timer event occurs. The counter causes a watchdog event after a specified time.
Bits 1 and 2 of the Module Status/Control register (815Dh) are cleared by a “warm reset”.
This keeps the watchdog timer from expiring on a “warm reset” that is not initiated from a
source other than a watchdog timeout. ENSYSO (bit 6 of 815Dh) also has to be cleared by
the BIOS must set the BTOE bit (the VME Bus Timeout Enable bit).
The watchdog timer is enabled by setting the WDTR bit (bit 3 of register 815Dh). Note
that a watchdog hardware reset results in a “warm” hardware reset. An I/O read to address
815D resets the counter.
To program the watchdog timer, follow these steps:
1. Determine if you want the watchdog timer to reset the EPC-8A or signal a watchdog
timer event using IRQ10. Use bit 3 in the Module Status/Control Register (815Dh). If
set to 1, the EPC-8A resets. If set to 0, the event is signaled.
2. Determine if you want the system to 1) halt or 2) continue rebooting on the watchdog
timer event. From the EPC-8A BIOS Advanced Menu, choose the option you prefer enabled.
3. Set the speed of your watchdog timer. Options are 8.2 seconds, 128 mS, or 1.02
seconds. Use bits 1 and 2 of register 815Dh. Bit 1 is the slow timer and bit 2 is the fast
timer. When used in conjunction, the settings are as follows:
01 8.2 seconds
10 128 mS
11 1.02 seconds
The timer is reset to its maximum value by an I/O read of the module status/control
register. Application software that utilizes this timer should take care to reset the counter
just prior to enabling the interrupt bit in register 8155h. This inhibits a spurious timer
event from occurring just after enabling the timer.