Specifications

EPC-8A Hardware Reference
74
Where a bit position has been described by a 0 or 1, the bit is a ROM bit, and writing to it
has no effect. Unless otherwise noted below, all registers and bit values are readable and
writeable.
Configuration (8102h)
This register controls VGA controller enables and the VMEbus interface. Only the lower four
bits in this register are cleared by an “AT reset” (that is, when the RESET button is pushed
or WDT reset occurs or SYSRESET occurs). All eight bits are cleared by a power-on reset.
VME-32 VME 32-bit enable. This bit is automatically set by the BusManager software
when using EPConnect. Please note the VMER bit (bit 5 of the VME Event
State register), if asserted, also disables this function, but does not clear the
VME-32 bit.
1 Enables VME access through the 32-bit addressing mechanism.
0 Disabled.
VME-E VME E-page enable. This bit is automatically set by the BusManager software
when using EPConnect. Please note the VMER bit (bit 5 of the VME Event
State register), if asserted, also disables this function, but does not clear the
VME-32 bit.
1 Enables VME access through the DOS “E page”.
0 The “E page” is available for DOS use.
VGA VGA enable. If set (1), this bit enables the VGA controller. This bit powers up clear
and if the BIOS detects another VGA controller in the system it is not set. Once this
bit is set via write of “1” to this register only a hardware reset can clear it.
GPO VGA General Purpose output control. This inversion of this bit is tied to pin 15
of the VGA connector through a 150 ohm resistor.
ARBPRI Arbitration priority. This defines the level at which the EPC-8A arbitrates for
the VMEbus:
RELM Bus release mode:
1 ROR (Release on Request), if set.
0 RONR (Release on No Request) The “fair requester” mode.
ARBM Arbitration mode. This bit is pertinent only if the EPC-8A is jumpered to be the
slot 1 controller.
1 Priority
0 Round Robin
ARBPRI RELM ARBM GPO VGA VME-E VME-32
This value... Means...
11 3
10 2
01 1
00 0