Specifications

EPC-8A Hardware Reference
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bit is then set if four rising edges of the SYSCLK signal are detected. This bit
is intended to be used to detect that SYSCLK is being generated on the
backplane.
READY This is a RAM bit defined by the VXI specification. In a VXIbus software
environment, if READY=1 and PASS=1, the EPC-8A is ready to accept
VXI-defined messages. This bit is read-only from the VME port and may be
read/written from the PC port. This bit is also held clear while the SRST bit is
asserted. When deasserting SRST via an I/O write to this register, a second
write is required to reassert the READY bit, since the READY bit is held in
reset until just after the first write completes.
PASS This bit is read-only from the VME port and may be read/written from the PC
port. This bit is also held clear while the SRST bit is asserted. When
deasserting SRST via an I/O write to this register, a second write is required to
reassert the PASS bit since the PASS bit is held in reset until just after the first
write completes.
1 The EPC-8A completed its self test successfully.
0 The Test LED on the EPC-8A front panel is lit.
NOSF SYSFAIL inhibit. If set, the EPC-8A does not assert the VMEbus SYSFAIL
line due to the PASS bit being cleared. If the PASS bit is clear and this bit is
clear, then SYSFAIL is asserted. SYSFAIL is also asserted when a Watchdog
timeout reset occurs, independent of the setting of this bit. This bit may be read/
written from both the VME and PC ports.
SRST Soft Reset. Setting this bit places the EPC-8A into the soft reset state. This bit
may be read/written from both the VME and PC ports.
MODID This read-only bit is connected to pin 30 in row A of the VMEbus P2
connector. If clear (0), it denotes that the pin is being pulled high. (This is used
in VXI systems for module identification.) Note, this bit is defined but not
implemented in the EPC-8A and always returns a value of 1. If future versions
of the product need this capability it can be provided by installing a resistor.
SYSR SYSRESET. The EPC-8A asserts the VME SYSRESET line while this bit is 1.
When using this bit, it is the software’s responsibility to ensure that the
VME-specified minimum assertion time of SYSRESET is met. This bit may
be read/written from the PC port, but is read-only from the VME port.
R A read/write bit that is available for software use (For example, SURM).
RESDET This bit is cleared by a hardware reset. Once this bit is written to “1” from the
PC-port (read-only from the VME port) it can only be set to zero by a hardware
reset. This bit is used by the firmware to determine if a software or hardware
reset is in progress and it set to “1” before any OS or application is invoked.
Reserved (8146h and 8147h)
These registers are reserved and return all ones if read.
Lower
11111111
Upper
11111111