Specifications

Appendix F: Registers
77
Protocol Register/Signal FIFO (8148h and 8149h)
A read of this register from either the PC or VME ports reads the ROM constants stored in
the protocol register. A write from either the PC or VME port writes the signal register.
The protocol register (the read value) defines the EPC-8A as being a servant and
commander, having a signal register, being a bus master and an interrupter, not providing
the shared-memory protocol, and not providing fast handshake mode.
When written from the VXIbus, this register is the signal register. The value written enters
the signal FIFO (two deep) or returns a bus error (BERR) if the FIFO is already full.
A write to the signal register is a happening of some significance for the EPC-8A, since it
potentially asserts an EPC interrupt, shuffles a signal-register FIFO, and may return BERR
if the FIFO is already full. For these reasons, the full semantics of writing to the signal
register are discussed separately in a later section.
Response Register (814Ah and 814Bh)
This register contains some VXI-defined state bits associated with message handling, and
several EPC-8A dependent bits. All of these bits may read/written (except where noted
below) from both the PC and VME ports. Some of this bits may also be cleared by certain
hardware events as described below.
DOR RAM bit available to software for VXI communication protocols.
DIR RAM bit available to software for VXI communication protocols.
ERR RAM bit available to software for VXI communication protocols.
RRDY Read ready. A 1 denotes that the message registers contain outgoing data to be
read by another device. RRDY is cleared when the message low register is
read.
WRDY Write ready. If set, the message registers are armed for an incoming message.
When a write occurs into the message-low register, WRDY is cleared and the
MSGR interrupt condition is asserted.
R RAM bit available to software.
RRIEN This EPC-8A specific bit is used to enable RRDY interrupt signaling.
0 Hardware reset state. only the deassertion of WRDY causes the
MSGR interrupt to be asserted.
1 The “OR” of the deasserted RRDY, WRDY bits is used to assert
the interrupt.
This bit would normally only be set for protocols that require multiple reply
data to be sent in response to a single command.
SIG If this EPC-8A specific bit is 0, the signal register FIFO is empty. This bit is
Lower
11111111
Upper
00011111
Lower
R RRIEN 1 SIG MCLK WRCP FSIG LSIG
Upper
0 1 DOR DIR ERR RRDY WRDY 1