Specifications

Appendix F: Registers

Reserved (814C and 814D)

These registers are reserved and return 1s when read. Writes to these registers have

no effect.

Message Low Register (814Eh and 814Fh)

There are actually two 16-bit registers at this address, outgoing and incoming 16 bit

registers (UART model).

• Outgoing register: A write from the PC side fills the outgoing register. This register

can only be read from the VME port and when this occurs the RRDY bit is deasserted

in the Response register.

• Incoming register: A read from the PC side reads the incoming register. The

incoming register can only be written to from the VME bus port and when this occurs,

the WRDY bit is deasserted in the Response register.

VME A31–24 Address Register (8150h)

This register is one of several that supply the VMEbus address bits when the EPC-8A

makes an access in its “E page.” This register supplies VME address bits A31–A24.

VME Modifier Register (8151h)

This register is also used when the EPC-8A makes an access through its E page to the

VMEbus. Bits 7 and 6 provide VME address bits A23 and A22, respectively. Bits 3–0

define the value placed on the associated VMEbus address-modifier lines. Register bits

are not defined for the VMEbus address-modifier AM3 and AM0 lines since, for all

defined address-modifier values in the VMEbus specification, AM3 is 1 and AM0 is the

inverse of AM1. Therefore these two bit values are generated by hardware. Note that

because AM3 and AM0 are hardware generated, the EPC-8A does not support

user-defined address-modifiers.

BORD Byte order. This bit controls the ordering of data bytes for D16 and D32

VMEbus accesses. If 0, the bytes are transmitted in little endian (Intel) order;

if 1, byte-swapping hardware transmits the bytes in big endian (Motorola)

order. Refer to the previous section in this chapter on byte ordering.

IACK This bit, when set, is used to define the VMEbus access as an interrupt

acknowledge cycle. The interrupt being acknowledged must be encoded by

software as a value on VME address lines A1–A3.

Lower

11111111

Upper

11111111

Lower

RAM

Upper

RAM

VMEbus A31

–24 Address register (WA31–24)

VME WA23

–22 BORD IACK AM5 AM4 AM2 AM1