Specifications

EPC-8A Hardware Reference

VME Interrupt State Register (8152h)

This read-only register defines the state of the VMEbus and message interrupts.

IRQx If clear (0), the associated VMEbus interrupt line is asserted.

MSGR If clear (0), a message interrupt is being signaled. MSGR is clear if both bits

RRDY and WRDY in the response register are clear.

VME Interrupt Enable Register (8153h)

This is a mask of the interrupt conditions in the interrupt state register. A 1 denotes that the

corresponding interrupt is enabled. If any bit in this register is a 1 and the corresponding

bit in the interrupt state register is a 0, the EPC-8A IRQ10 interrupt is asserted. Software

may then examine the interrupt and event state registers to determine the cause.

VME Event State Register (8154h)

Similar to the interrupt state register, this register defines additional conditions that may

result in an IRQ10 interrupt. If the bit is 0, the condition is present. All bits are read-only

except for the VMER and BERR signals.

ACFA VMEbus ACFAIL is asserted.

BERR This bit is cleared (asserted low) when an access from the EPC-8A to the

VMEbus is terminated with a BERR (bus error). It is also held clear when the

SRST bit is set. This bit may be deasserted by writing a “1” (provided SRST is

not asserted) into this bit position.

SYSF VMEbus SYSFAIL is asserted.

WDT Watchdog timer expired

VMER A SYSRESET or soft reset has occurred. This bit is held clear while

SYSRESET is asserted or the SRST bit is asserted. This bit may be deasserted

by writing a “1” into it once the reset conditions are removed.

SIGR Signal register FIFO is not empty.

All bits are read-only except BERR and VMER. BERR is a sticky bit that is cleared

whenever an access from the EPC-8A is terminated by a bus error or is held clear, and

remains clear (0) unless changed by software (by writing any value to this register).

VME Event Enable Register (8155h)

The low-order six bits are a mask of the interrupt conditions in the event state register. A 1

denotes that the corresponding event is enabled as an interrupt. If any bit in this register is

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR

1 1 VMER SIGR WDT ACFA BERR SYSF