Specifications

Appendix F: Registers
81
a 1 and the corresponding bit in the event state register is a 0, the EPC-8A IRQ10 interrupt
is asserted. Software may then examine the interrupt and event state registers to determine
the cause.
VME Interrupt Generator Register (8158h)
This register is used to assert one of the VMEbus interrupt signals. If the
INTERRUPT-OUT bits are zero, no interrupt line is asserted by the EPC-8A. If lower
three bits are set to 001, VMEbus IRQ1 is asserted. If set to 010, VMEbus IRQ2 is
asserted, and so on. If and when an interrupt acknowledge is sent to the EPC-8A, the
INTERRUPT-OUT bits are cleared. You can also deassert a previously asserted interrupt
by writing 0 into the register. Finally, this register is cleared whenever SYSRESET* is
asserted or when the SRST (soft reset) bit is asserted.
Bit 7 of register 8158 is read-only and returns the value of the slot1 jumper setting. If the
slot 1 shunt is installed (slot1 operation), then 0 is returned. If the slot1 shunt is not
installed, then 1 is returned.
Unique Logical Address Register (815Ch)
This register contains the EPC-8A’s ULA. The ULA contents are used to map the
EPC-8A’s register set into VME A16 space as described below in the VMEbus Mapped
Registers section. The ULA is changed by writing into this register or into the ID register.
Module Status/Control Register (815Dh)
This register contains the following miscellaneous status and control bits: Only bit 3,
WDTR, is cleared by a warm reset. All bits of this register, except for the read-only DONE
status bit, are cleared by a power-on reset.
DONE This read-only bit is 0 whenever the EPC-8A has a VMEbus access
outstanding. It is used for determining when a pipelined VMEbus write is
complete.
BTOE Bus timeout enable. Enables the slot-0 bus timeout timer. This is used by the
BIOS.
WDTR Watchdog timer reset enable. If 1, expiration of the watchdog timer generates
a reset of the EPC-8A. If 0, only the WDT event is signaled. A read of the
module status register should be performed before enabling the watchdog
timer reset. This clears the watchdog counter to zero so that a PC reset does not
occur immediately after enabling the watchdog timer reset.
FWDT Fast watchdog timer.
SWDT Slow watchdog timer. FWDT and SWDT produce the following timeout
values:
SLOT1*1111 INTERRUPT-OUT
ULA
DONE 0 1 BTOE WDTR FWDT SWDT 1