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CLC001

Serial Digital Cable Driver with Adjustable Outputs

General Description

The CLC001 is a monolithic, high-speed cable driver

designed for use in SMPTE 259M serial digital video and

ITU-T G.703 serial digital data transmission applications.

The CLC001 drives 75Ω transmission lines (Belden 8281 or

equivalent) at data rates up to 622 Mbps. Controlled output

rise and fall times (400 ps typical) minimize transition-

induced jitter. The output voltage swing is adjustable from

800 mV

p-p

to 1.0 V

p-p

using an external resistor.

The CLC001’s output stage consumes less power than other

designs. The differential inputs accept LVDS signal levels,

LVPECL levels directly or PECL with attenuation networks.

All these make the CLC001 an excellent general purpose

high speed driver for high-speed, long distance data

transmission applications.

The CLC001 is powered from a single +3.3V supply and

comes in a small 8-pin SOIC package.

Key Specifications

n 400 ps rise and fall times

n Data rates to 622 Mbps

n 100 mV differential input threshold

n Low residual jitter

Features

n Adjustable output amplitude

n Differential input and output

n Accepts LVPECL or LVDS input swings

n Low power dissipation

n Single +3.3V supply

Applications

n Digital routers and distribution amplifiers

n Coaxial cable driver for digital transmission lines

n Twisted pair driver

n Serial digital video interfaces for the commercial and

broadcast industry

n SMPTE, Sonet/SDH, and ATM compatible driver

n Buffer applications

Connection Diagram (8-Pin SOIC)

Typical Application

DS101329-10

622 Mbps Eye Pattern with STM-4 Signal Mask

DS101329-2

Order Number CLC001AJE

See NS Package Number M08A

DS101329-1

March 2001

CLC001 Serial Digital Cable Driver with Adjustable Outputs

Summary of content (10 pages)

PAGE 1
CLC001 Serial Digital Cable Driver with Adjustable Outputs General Description Applications The CLC001 is a monolithic, high-speed cable driver designed for use in SMPTE 259M serial digital video and ITU-T G.703 serial digital data transmission applications. The CLC001 drives 75Ω transmission lines (Belden 8281 or equivalent) at data rates up to 622 Mbps. Controlled output rise and fall times (400 ps typical) minimize transitioninduced jitter. The output voltage swing is adjustable from 800 mVp-p to 1.
PAGE 2
CLC001 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
PAGE 3
CLC001 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (Note 3) Symbol Parameter tr, tf Rise time, Fall time tos Output overshoot tjit Output jitter tpd Propagation delay Conditions Min 20%–80%, (Notes 4, 5) Typ Max Units 400 800 ps 5 % (Note 7) 25 ps (Note 5) 1.9 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.
PAGE 4
CLC001 Test Loads (Continued) DS101329-3 FIGURE 2. Test Circuit Pin Descriptions Pin # Name Description 1 VBB Optional, bias voltage (may be used to bias inputs) - see device operation section for details. If unused leave as no connect (NC). 2 VIN+ Positive input pin 3 VIN- Negative input pin 4 RREF Output driver level control. Connect a resistor to ground to set output voltage swing.
PAGE 5
CLC001 Device Operation INPUT INTERFACING Numerous input configurations exist for applying PECL, LVPECL, and LVDS signals to the input of the CLC001. Inputs may be single-ended or differential, AC or DC coupled. The VBB pin may be used to provide a DC bias voltage to the inputs. Leave this pin as a no connect when no bias is needed. Note that DC-coupled inputs such as direct LVDS and LVPECL connections are self-biasing and do not require use of the VBB pin.
PAGE 6
CLC001 Device Operation with 825Ω gives the equivalent termination resistance of 75Ω. RBB set at 5kΩ provides 1.25V of DC bias to the input. (Continued) Figure 5 shows the CLC001 with an AC-coupled, single ended input connection. The 82.5Ω resister in parallel DS101329-5 FIGURE 5. Single Ended 75Ω Coaxial Cable, AC-coupled A typical DC-coupled, twisted pair cable connection is shown in Figure 6. The CLC001 is driven differentially.
PAGE 7
termination used in conjunction with two 50Ω resistors to filter common mode noise. RBB set at 5kΩ provides 1.25V of DC bias to each input. (Continued) Figure 7 shows an AC-coupled, twisted pair cable application. It implements a center tap capacitance DS101329-7 FIGURE 7. Twisted Pair Cable, AC-coupled PECL or LVPECL drivers may be interfaced to the CLC001 as shown in Figure 8. The voltage divider network will reduce the PECL output to the proper levels.
PAGE 8
CLC001 Device Operation 120Ω. This resistor should be located close to the CLC001 inputs pins to minimize the resulting stub length between the resistor and device pads. The CLC001 supports ± 100mV thresholds across the entire LVDS common mode range of 0.1V to 2.3V for a 200mV differential signal. (Continued) A typical LVDS input connection is shown in Figure 9. The media is driven differentially by an LVDS driver.
PAGE 9
Evaluation Board (Continued) Evaluation boards are available for a nominal charge that demonstrate the basic operation of the SDI/SDV/SDH devices. The evaluation boards can be ordered through National’s Distributors. Supplies are limited, please check for current availability. OUTPUT INTERFACING The CLC001 has two complementary, ground referenced outputs designed to drive AC-coupled and terminated 75Ω coaxial cables.
PAGE 10
CLC001 Serial Digital Cable Driver with Adjustable Outputs Physical Dimensions inches (millimeters) unless otherwise noted Order Number CLC001AJE NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.