User Manual

DS2401
7 of 10
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
480ms £ t
RSTL
< ¥ *
480ms £ t
RSTH
< ¥ (includes recovery time)
15ms £ t
PDH
< 60ms
60ms £ t
PDL
< 240ms
* In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
RSTL
+ t
R
should always
be less than 960ms.
READ/WRITE TIMING DIAGRAM Figure 6
Write-One Time Slot
60ms £ t
SLOT
< 120ms
1ms £ t
LOW1
< 15ms
1ms £ t
REC
< ¥
RESISTOR
MASTER
RESISTOR
MASTER
DS2401