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DS8024

Smart Card Interface

________________________________________________________________

Maxim Integrated Products

Rev 1; 8/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS8024 smart card interface IC is a low-cost, analog

front-end for a smart card reader, designed for all ISO

7816, EMV*, and GSM11-11 applications. The DS8024 is

a pin-for-pin drop-in replacement for the NXP TDA8024

and is offered in 28-pin TSSOP and SO packages.

Applications requiring support for 1.8V smart cards or

requiring low power should consider the DS8113, which

achieves lower active- and stop-mode power with mini-

mal changes to application hardware and software.

Applications

Set-Top Box Conditional Access

Access Control

Banking Applications

POS Terminals

Debit/Credit Payment Terminals

PIN Pads

Automated Teller Machines

Telecommunications

Pay/Premium Television

Features

♦ Analog Interface and Level Shifting for IC Card

Communication

♦ 8kV (min) ESD (IEC) Protection on Card Interfaces

♦ Internal IC Card Supply-Voltage Generation:

5.0V ±5%, 80mA (max)

3.0V ±8%, 65mA (max)

♦ Automatic Card Activation and Deactivation

Controlled by Dedicated Internal Sequencer

♦ I/O Lines from Host Directly Level Shifted for

Smart Card Communication

♦ Flexible Card Clock Generation, Supporting

External Crystal Frequency Divided by 1, 2, 4, or 8

♦ High-Current, Short-Circuit and High-Temperature

Protection

Ordering Information

Note: Contact the factory for availability of other variants and

package options.

Denotes a lead-free/RoHS-compliant package.

*EMV is a trademark owned by EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for details.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be

simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata

PART TEMP RANGE PIN-PACKAGE

DS8024-RJX+ -40°C to +85°C 28 TSSOP

DS8024-RRX+ -40°C to +85°C 28 SO

Selector Guide appears at end of data sheet.

PGND

AUX2IN

AUX1IN

I/OIN

XTAL2

TOP VIEW

DS8024

XTAL1

OFF

GND

21 V

20 RSTIN

19 CMDVCC

18 N.C.

17 V

16 RST

15 CLK

5V/3V

CLKDIV2

CLKDIV1

CP1

DDA

PRES

I/O

AUX2

AUX1

14CGND

CP2

SO/TSSOP

Pin Configuration

Summary of content (15 pages)

PAGE 1
Rev 1; 8/08 Smart Card Interface The DS8024 smart card interface IC is a low-cost, analog front-end for a smart card reader, designed for all ISO 7816, EMV*, and GSM11-11 applications. The DS8024 is a pin-for-pin drop-in replacement for the NXP TDA8024 and is offered in 28-pin TSSOP and SO packages. Applications requiring support for 1.8V smart cards or requiring low power should consider the DS8113, which achieves lower active- and stop-mode power with minimal changes to application hardware and software.
PAGE 2
DS8024 Smart Card Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on VDD Relative to GND ...............-0.5V to +6.5V Voltage Range on VDDA Relative to PGND ...........-0.5V to +6.5V Voltage Range on CP1, CP2, and VUP Relative to PGND...............................................-0.5V to +7.5V Voltage Range on All Other Pins Relative to GND......................................-0.5V to (VDD + 0.5V) Maximum Junction Temperature .....................................
PAGE 3
Smart Card Interface (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RST PIN Card-Inactive Mode Card-Active Mode Output Low Voltage VOL_RST1 IOL_RST = 1mA 0 0.3 V Output Current IOL_RST1 VO_LRST = 0V 0 -1 mA Output Low Voltage VOL_RST2 IOL_RST = 200μA 0 0.3 V Output High Voltage VOH_RST2 IOH_RST = -200μA VCC 0.5 VCC V Rise Time tR_RST CL = 30pF (Note 3) 0.
PAGE 4
DS8024 Smart Card Interface RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.
PAGE 5
Smart Card Interface (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V) Input Low Voltage VIL -0.3 0.3 x VDD V Input High Voltage VIH 0.7 x VDD VDD + 0.3 V Input Low Current IIL_IO 5 μA Input High Current IIH_IO Integrated Pullup Resistor 0 < VIL < VDD 0 < VIH < VDD RPU Pullup to VDD, 5V/3V only VOL IOL = 2mA 50 85 5 μA 120 k 0.
PAGE 6
Smart Card Interface DS8024 Pin Description 6 PIN NAME 1, 2 CLKDIV1, CLKDIV2 FUNCTION 3 5V/3V 5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects 5V operation; logic-low selects 3V operation. See Table 3 for a complete description of choosing card voltages. 4 PGND Analog Ground 5, 7 CP2, CP1 6 VDDA 8 VUP 9 PRES Card Presence Indicator. Active-low card presence inputs.
PAGE 7
Smart Card Interface The DS8024 is an analog front-end for communicating with 3V and 5V smart cards. Using an integrated charge pump, the DS8024 can operate from a single input voltage. The device translates all communication lines to the correct voltage level and provides power for smart card operation. It can operate from a wide input voltage range (3.3V to 6.0V). The DS8024 is compatible with the NXP TDA8024 and is provided in the same packages. (Note that the PORADJ pin is not present in the DS8024.
PAGE 8
DS8024 Smart Card Interface The DS8024 card interface remains inactive no matter the levels on the command lines until duration tW after VDD has reached a level higher than VTH2 + VHYS2. When VDD falls below VTH2, the DS8024 executes a card deactivation sequence if its card interface is active. Clock Circuitry The clock signal from the DS8024 to the smart card (CLK) is generated from the clock input on XTAL1 or from a crystal operating at up to 20MHz connected between pins XTAL1 and XTAL2.
PAGE 9
Smart Card Interface An alternate sequence allows the application to control when the clock is applied to the card. 1) Host: Set RSTIN high. 2) Host: Set CMDVCC low. 3) Host: Set RSTIN low between t3 and t5; CLK will now start. 4) DS8024: RST stays low until t5, then RST becomes the copy of RSTIN. 5) DS8024: RSTIN has no further effect on CLK after t5. If the applied clock is not needed, set CMDVCC low with RSTIN low.
PAGE 10
DS8024 Smart Card Interface CMDVCC VCC ATR I/O CLK 200ns RSTIN RST I/OIN t0 t1 t2 t3 t4 t5 = tACT Figure 4. Activation Sequence at t3 CMDVCC RST CLK I/O VCC t10 t12 t13 t14 t15 tDE Figure 5.
PAGE 11
Smart Card Interface When the host microcontroller is done communicating with the smart card, it sets the CMDVCC line high to execute an automatic deactivation sequence and returns the card interface to the inactive mode. The following sequence of events occurs during a deactivation sequence (Figure 5): 1) RST goes low (t10). 2) CLK is held low (t12 = t10 + 0.5 × T), where T is 64 times the period of the internal oscillator (approximately 25µs). 3) I/O, AUX1, and AUX2 are pulled low (t13 = t10 + T).
PAGE 12
DS8024 Smart Card Interface PRES OFF CMDVCC DEBOUNCE DEBOUNCE VCC DEACTIVATION CAUSED BY CARDS WITHDRAWAL DEACTIVATION CAUSED BY SHORT CIRCUIT Figure 6. Behavior of PRES, OFF, CMDVCC, and VCC OFF PRES RST CLK I/O VCC t10 t12 t13 t14 t15 tDE Figure 7.
PAGE 13
Smart Card Interface DS8024 VDD 100nF 33pF 33pF +3.3V 100nF 100nF +3.3V 100nF XTAL1 GPIO ... XTAL2 GND CP2 VUP VDD CP1 +10μF PGND VDDA CLKDIV1 CLKDIV2 5V/3V PRES VCC ... ... ... GPIO ISOIO0 100kΩ OFF RSTIN CMDVCC AUX2IN AUX1IN I/OIN RST CLK I/O AUX1 AUX2 DS8024 100nF* 220nF* 100nF* 220nF* CGND MAXQ1103 GPIO ... ... ...
PAGE 14
DS8024 Smart Card Interface Applications Information Performance can be affected by the layout of the application. For example, an additional cross-capacitance of 1pF between card reader contacts C2 (RST) and C3 (CLK) or C2 (RST) and C7 (I/O) can cause contact C2 to be polluted with high-frequency noise from C3 (or C7). In this case, include a 100pF capacitor between contacts C2 and CGND.
PAGE 15
Smart Card Interface REVISION NUMBER REVISION DATE 0 6/08 Initial release. — 1 8/08 Clarified the VDDA specification in the Recommended DC Operating Conditions table. 2 DESCRIPTION PAGES CHANGED EMVCo approval of the interface module (IFM) contained in this Terminal shall mean only that the IFM has been tested in accordance and for sufficient conformance with the EMV Specifications, Version 3.1.1, as of the date of testing.