FBDIMM DDR2 SDRAM DDR2 Fully Buffered DIMM 240pin FBDIMMs based on 1Gb Q-die 60FBGA with Lead-Free and Halogen-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
FBDIMM DDR2 SDRAM Table of Contents 1.0 FEATURES .....................................................................................................................................4 2.0 FBDIMM GENERALS .....................................................................................................................5 2.1 FB-DIMM Operation Overview ........................................................................................................5 ..................................................
FBDIMM DDR2 SDRAM Revision History Revision Month Year History 1.0 March 2008 - Initial Spec. Release 1.1 March 2008 - Added 4Rank Products based on Low Power AMB 1.11 March 2008 - Corrected Typo 1.12 April 2008 - Corrected mechanical Dimension 1.2 August 2008 - Changed the ordering information 1.3 December 2008 - Updated the IDD current specification 1.4 May 2009 - Added new products on the line-up (Based on Montage D3 AMB) 3 of 42 Rev. 1.
FBDIMM DDR2 SDRAM 1.0 Features - - 240pin fully buffered dual in-line memory module (FBDIMM) - 3.2Gb/s, 4.0Gb/s link transfer rate - 1.8V +/- 0.1V Power Supply for DRAM VDD/VDDQ - 1.5V +0.075/-0.045V Power Supply for AMB VCC - 3.3V +/- 0.3V Power Supply for VDDSPD - Buffer Interface with high-speed differential point-topoint Link at 1.
FBDIMM DDR2 SDRAM 2.0 FBDIMM Generals 2.1 FBDIMM Operation Overview FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited density build-up as channel speeds increase with memory system having the stub-bus architecture.
FBDIMM DDR2 SDRAM 2.2 FBDIMM Channel Frequency Scaling There are many frequency parameters including reference clock frequency, DRAM clock frequency, DRAM data transfer rate, channel transfer rate and channel unit interval. All of frequency parameters are scaled with a certain gear ratio. External clock source provides reference clock input to AMB and Host. External clock source is relatively slower than channel and DRAM frequency.
FBDIMM DDR2 SDRAM 2.3 FBDIMM Clocking Scheme In FB-DIMM platform design, phase adjustment among reference clock inputs to each individual AMB and host is not taken account. Thus, clock synchronization is made by using both external reference clock and channel data stream in FB-DIMM memory system. Host and each individual AMB has a each individual IO basis clock recovery circuitry for channel data communication. It runs with inputs from PLL inside chip and data stream from the other AMB or Host.
FBDIMM DDR2 SDRAM Southbound Command Frame Format* Bit Transfer 0 1 2 3 4 5 6 7 8 9 10 11 9 aE0 aE1 aE2 aE3 FE21 FE20 FE19 FE18 FE17 FE16 FE15 FE14 8 aE7 aE6 aE5 aE4 0 0 0 0 0 0 0 0 7 6 5 4 3 2 aE8 F0=0 aC20 aC16 aC12 aC8 aE9 F1=0 aC21 aC17 aC13 aC9 aE10 aE13 aC22 aC18 aC14 aC10 aE11 aE12 aC23 aC19 aC15 aC11 0 0 bC20 bC16 bC12 bC8 0 0 bC21 bC17 bC13 bC9 0 0 bC22 bC18 bC14 bC10 0 0 bC23 bC19 bC15 bC11 0 0 cC20 cC16 cC12 cC8 0 0 cC21 cC17 cC13 cC9 0 0 cC22 cC18 cC14 cC10 0 0 cC23 cC19 cC15 cC11 FE0 FE1
FBDIMM DDR2 SDRAM 2.6 Basic Timing Diagram 1 FBD southbound cmd/data 2 3 4 ACT1 NOP NOP 5 6 7 8 9 10 11 12 13 RD1 NOP NOP DIMM 1 cmd ACT1 RD1 DIMM 1 data DIMM 2 cmd DIMM 2 data FBD northbound data Figure 7. Basic DRAM Read Data Transfers on FBD 1 FBD southbound cmd/data DIMM 1 cmd 2 ACT1 NOP NOP 3 4 ACT2 NOP NOP RD1 NOP NOP ACT1 5 6 7 8 9 10 11 12 13 RD2 NOP NOP RD1 DIMM 1 data DIMM 2 cmd ACT2 RD2 DIMM 2 data FBD northbound data No Bubble Figure 8.
FBDIMM DDR2 SDRAM 1 FBD southbound cmd/data 2 3 ACT1 NOP NOP DIMM 1 cmd 4 5 6 7 8 9 10 11 12 13 NOP WR1 NOP NOP SYNC Wdata Wdata Wdata Wdata 1010 Wdata Wdata Wdata Wdata 0101 ACT1 WR1 Fixed fall through time DIMM 1 data DIMM 2 cmd DIMM 2 data FBD northbound data Status Figure 9.
FBDIMM DDR2 SDRAM 2.
FBDIMM DDR2 SDRAM 2.8 Interfaces Figure 12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FBD links, one DDR2 channel and an SMBus interface. Each FBD link connects the Advanced Memory Buffer to a host memory controller or an adjacent FBD.
FBDIMM DDR2 SDRAM 3.3 FBD Channel Latency FBD channel latency is measured from the time a read request is driven on the FBD channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory controller. When not using the Variable Read Latency capability, the latency for a specific FBDIMM on an FBD channel is always equal to the latency for any other FBDIMM on that channel.
FBDIMM DDR2 SDRAM 4.
FBDIMM DDR2 SDRAM [ Table 5 ] Pin Description Pin Name Type Pin Description Pin Numbers SCK Input System Clock Input, positive line 228 SCK Input System Clock Input, negative line 229 PN[13:0] Output Primary northbound Data, positive lines 22, 25, 28, 31, 34, 37, 40, 48, 51, 54, 57, 60, 63, 66 PN[13:0] Output Primary northbound Data, negative lines 23, 26, 29, 32, 35, 38, 41, 49, 52, 55, 58, 61, 64, 67 PS[9:0] Input Primary Southbound Data, positive lines 70, 73, 76, 79, 82, 90, 93,
FBDIMM DDR2 SDRAM 5.0 FBDIMM Functional Block Diagram 5.
FBDIMM DDR2 SDRAM 5.
FBDIMM DDR2 SDRAM 5.
FBDIMM DDR2 SDRAM 5.
FBDIMM DDR2 SDRAM DQS5 DQS5 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S0 S1 S2 S3 DM/ NU/ DQS DQS CS RDQS RDQS DM/ NU/ DQS DQS CS RDQS RDQS DM/ NU/ DQS DQS CS RDQS RDQS DM/ NU/ DQS DQS CS RDQS RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D14 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D23 D32 DQS6 DQS6 DQS15 DM/ NU/ DQS DQS CS RDQS RDQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 D
FBDIMM DDR2 SDRAM 5.
FBDIMM DDR2 SDRAM VSS S1 S3 S0 S2 DQS4 DQS4 DM DQ32 DQ33 DQ34 DQ35 DQS13 DQS13 CS I/O 0 I/O 1 I/O 2 I/O 3 D9 DM DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQ40 DQ41 DQ42 DQ43 DQS10 DQS10 D15 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CB4 CB5 CB6 CB7 D14 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQ60 DQ61 DQ62 DQ63 DQS17 DQS17 D13 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQ56 DQ57 DQ58 DQ59 DQS16 DQS16 D12 CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQ52 DQ53 DQ54 DQ55
FBDIMM DDR2 SDRAM 6.0 Electrical Characteristics [ Table 6 ] Absolute Maximum Ratings Symbol MIN MAX Units Note Voltage on any pin relative to VSS Parameter VIN, VOUT -0.3 1.75 V 1 Voltage on VCC pin relative to VSS VCC -0.3 1.75 V 1 Voltage VDD pin relative to VSS VDD -0.5 2.3 V 1 Voltage on VTT pin relative to VSS VTT -0.5 2.
FBDIMM DDR2 SDRAM [ Table 9 ] Power specification parameter and test condition Symbol Icc_Idle_0 Idd_Idle_0 Conditions Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary Channel Disabled CKE high. Command and address lines stable. DRAM clock active. Power Supply Units @1.5V mA @1.8V mA @1.5V mA @1.8V mA @1.5V mA @1.8V mA @1.5V mA @1.
FBDIMM DDR2 SDRAM [ Table 10 ] Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V) 1GB(M395T2863QZ4) Symbol E66 E65 E68 F76 F78 (PC2-5300) E76 Notes Unit (PC2-6400) Icc_Idle_0 2600 2600 1600 3200 1700 3200 @1.5V mA Idd_Idle_0 970 970 770 1070 770 1070 @1.8V mA P_idle_0 5.94 5.94 3.98 7.07 4.14 7.07 Icc_Idle_1 3400 3400 2300 4200 2500 4200 @1.5V mA Idd_Idle_1 970 970 770 1070 770 1070 @1.8V mA P_idle_1 7.20 7.20 5.09 8.65 5.40 8.
FBDIMM DDR2 SDRAM (Vdd Max = 1.900V, Vcc Max = 1.575V) 4GB(M395T5160QZ4) Symbol E66 E65 E68 E63 F76 (PC2-5300) E76 Notes Unit (PC2-6400) Icc_Idle_0 2600 2600 1700 1500 3200 3200 @1.5V mA Idd_Idle_0 1980 1980 1580 1580 2080 2080 @1.8V mA P_idle_0 7.86 7.86 5.68 5.36 8.99 8.99 Icc_Idle_1 3400 3400 2600 1900 4200 4200 @1.5V mA W Idd_Idle_1 1980 1980 1580 1580 2080 2080 @1.8V mA P_idle_1 9.12 9.12 7.10 5.99 10.57 10.
FBDIMM DDR2 SDRAM (Vdd Max = 1.900V, Vcc Max = 1.575V) 8GB(M395T1G60QJ4) Symbol E68 F78 (PC2-5300) (PC2-6400) Notes Unit Icc_Idle_0 1700 1900 @1.5V mA Idd_Idle_0 2660 2660 @1.8V mA P_idle_0 7.73 8.05 Icc_Idle_1 2600 2800 @1.5V mA W Idd_Idle_1 2660 2660 @1.8V mA P_idle_1 9.15 9.46 W Icc_active_1 3200 3600 @1.5V mA Idd_active_1 5001 5241 @1.8V mA P_active_1 14.54 15.63 Icc_active_2 2600 2800 @1.5V mA Idd_active_2 2660 2660 @1.8V mA P_active_2 9.
FBDIMM DDR2 SDRAM [ Table 11 ] VTT Currents Symbol Typ MAX Units Idle current, DDR2 SDRAM device power down Description ITT1 500 700 mA Active power, 50% DDR2 SDRAM BW ITT2 500 700 mA [ Table 12 ] Reference Clock Input Specifications Parameter Symbol Reference clock frequency @3.2 Gb/s (nominal 133.33 MHz) Reference clock frequency @4.0 Gb/s (nominal 166.67 MHz) Rise time, fall time Values Units Note 133.40 MHz 1.2 158.33 166.75 MHz 1.
FBDIMM DDR2 SDRAM [ Table 13 ] Differential Transmitter Output Specifications Parameter Symbol Differential peak-to-peak output voltage for large voltage swing Values Units Comments mV EQ1, Note1 800 mV EQ1, Note1 520 mV EQ1, Note1 375 mV EQ2, Note1 135 280 mV EQ2, Note1,2 VTX-DE-3.5-Ratio -3.0 -4.0 dB 1,3,4 De-emphasized differential output voltage ratio for -6.0 dB de-emphasis VTX-DE-6.0-Ratio -5.0 -7.
FBDIMM DDR2 SDRAM [ Table 14 ] Differential Receiver Input Specifications Parameter Symbol Values Units Comments TBD mV EQ 5, Note1 MIN MAX 170 Differential peak-to-peak input voltage for large voltage swing VRX-DIFFp-p Maximum single-ended voltage in El condition VRX-IDLE-SE 75 mV 2,3 Maximum single-ended voltage in Ei condition (DC only) VRX-IDLE-SE-DC 50 mV 2,3 Maximum peak-to-peak differential voltage in El condition VRX-IDLE-DIFFp-p 65 mV 3 900 mV 4 mV 4,5 Single-ende
FBDIMM DDR2 SDRAM 11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak to peak common mode specification. For example, if VRX-DIFFp-p is 200 mV, the maximum AC peak-to peak common mode is the lesser of (200 mV*0.45=90 mV)and VRX-CM-AC-p-p. 12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed. 13.
FBDIMM DDR2 SDRAM 7.0 CHANNEL INITIALIZATION This chapter defines the process of initializing the FBD channel. The FBD initialization process generally follows the top to bottom sequence of state transitions shown in the high level AMB Initialization Flow diagram in Figure The host must sequence the AMB devices through the Disable, (back to Disable), Training, Testing, and Polling states in order to transition the AMBs into the active channel L0 state.
FBDIMM DDR2 SDRAM 8.0 Physical Dimensions : 8.1 128Mbx8 based 128Mx72 Module (1 Rank) 133.35 126.85 2x 3.25 4x 3.00 ± 0.1 2x 2.50 MIN AMB e c 2x DIA. 2.0 +0.1/-0 b a 67 5.175 9.50 18.80 2.0 30.35 ± 0.15 d 51 123 1.19 R0.75 R0.595 2.25 1.19 0.8 ± 0.05 3.9 1.19 120° 2.25 6.0 2.6 2.50 0.20 ± 0.15 2.50 2.50 ± 0.20 5.0 3.80 1.50 DETAIL a MAX 0.178 1.00 DETAIL b 1.25 R0.595 DETAIL c 33 of 42 DETAIL d DETAIL e Rev. 1.
FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units : Millimeters 8.2 max 30.35 ± 0.15 133.35 67 51 1.27 ± 0.10 123 34 of 42 Back 3.0 max Rev. 1.
FBDIMM DDR2 SDRAM 8.2 128Mbx8 based 256Mx72 Module (2 Ranks) M395T5663QZ4 133.35 126.85 2x 3.25 4x 3.00 ± 0.1 2x 2.50 MIN AMB e c 2x DIA. 2.0 +0.1/-0 b a 67 5.175 9.50 18.80 2.0 30.35 ± 0.15 d 51 123 1.19 R0.75 R0.595 2.25 1.19 0.8 ± 0.05 3.9 1.19 120° 2.25 6.0 2.6 2.50 0.20 ± 0.15 2.50 2.50 ± 0.20 5.0 3.80 1.50 DETAIL a MAX 0.178 1.00 DETAIL b 1.25 R0.595 DETAIL c 35 of 42 DETAIL d DETAIL e Rev. 1.
FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units : Millimeters 8.2 max 30.35 ± 0.15 133.35 67 51 1.27 ± 0.10 123 36 of 42 Back 3.0 max Rev. 1.
FBDIMM DDR2 SDRAM 8.3 256Mbx4 based 512Mx72 Module (2 Ranks) M395T5160QZ4 133.35 126.85 2x 3.25 4x 3.00 ± 0.1 2x 2.50 MIN AMB c e b a 2x DIA. 2.0 +0.1/-0 67 5.175 9.50 18.80 2.0 30.35 ± 0.15 d 51 123 1.19 R0.75 R0.595 2.25 1.19 3.9 0.8 ± 0.05 1.19 120° 2.25 6.0 2.6 0.20 ± 0.15 2.50 2.50 ± 0.20 5.0 2.50 3.80 1.50 DETAIL a MAX 0.178 1.00 DETAIL b 1.25 R0.595 DETAIL c 37 of 42 DETAIL d DETAIL e Rev. 1.
FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units : Millimeters 8.2 max 30.35 ± 0.15 133.35 67 51 1.27 ± 0.10 123 38 of 42 Back 3.0 max Rev. 1.
FBDIMM DDR2 SDRAM 8.4 128Mbx8 based 512Mx72 Module (4 Ranks) M395T5163QZ4 133.35 126.85 2x 3.25 4x 3.00 ± 0.1 2x 2.50 MIN AMB c e b a 2x DIA. 2.0 +0.1/-0 67 5.175 9.50 18.80 2.0 30.35 ± 0.15 d 51 123 1.19 R0.75 R0.595 2.25 1.19 3.9 0.8 ± 0.05 1.19 120° 2.25 6.0 2.6 0.20 ± 0.15 2.50 2.50 ± 0.20 5.0 2.50 3.80 1.50 DETAIL a MAX 0.178 1.00 DETAIL b 1.25 R0.595 DETAIL c 39 of 42 DETAIL d DETAIL e Rev. 1.
FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units : Millimeters 8.2 max 30.35 ± 0.15 133.35 67 51 1.27 ± 0.10 123 40 of 42 Back 3.0 max Rev. 1.
FBDIMM DDR2 SDRAM 8.5 256Mbx4 based 1Gx72 Module (4 Ranks) M395T1G60QJ4 133.35 126.85 2x 3.25 4x 3.00 ± 0.1 2x 2.50 MIN AMB c e b a 2x DIA. 2.0 +0.1/-0 67 5.175 9.50 18.80 2.0 30.35 ± 0.15 d 51 123 1.19 R0.75 R0.595 2.25 1.19 3.9 0.8 ± 0.05 1.19 120° 2.25 6.0 2.6 0.20 ± 0.15 2.50 2.50 ± 0.20 5.0 2.50 3.80 1.50 DETAIL a MAX 0.178 1.00 DETAIL b 1.25 R0.595 DETAIL c 41 of 42 DETAIL d DETAIL e Rev. 1.
FBDIMM DDR2 SDRAM Heat Spreader Design Guide Units : Millimeters 8.2 max 30.35 ± 0.15 133.35 67 51 1.27 ± 0.10 123 42 of 42 Back 3.0 max Rev. 1.