Datasheet

Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
11 of 42
2.7 Advanced Memory Buffer Block Diagram
Figure 11. Advanced Memory Buffer Block Diagram
Advance Memory Buffer
Block Diagram
demux
Data Merge
Re-synch
PISO
Re-Time
10x2
Southbound
Data In
10x2
Southbound
Data Out
4
NORTH
PLL
1x2
Ref Clock
Reset
Control
Reset#
10*2 10*2
Link Init SM
and Control
and CSRs
mux
lnit
patterns
IBIST - TX
IBIST - RX
failover
Command
Decoder &
CRC Check
Thermal
Sensor
LAI Logic
mux mux
DDR State
Controller
and CSRs
36
deep
Write
Data
FIFO
External MEMBIST
DDR calibration &
DDR IOBIST/DFX
Core Control
and CSRs
Data CRC Gen
& Read FIFO
Cmd Out
Data Out
Data In
Sync & ldie
Pattern
Generator
NB LAI Buffer
mux
IBIST -TX IBIST - RX
demux
Data Merge
Re-synch
PISO
Re-Time
14x2
Data Out
Northbound
14*1214*6*2
failover
Link lnit SM
and Control
and CSRs
14x2
Data In
Northbound
SMbus
Controller
SMbus
LAI
Controller
DDR
IOs
DRAM Clock
4
DRAM Clock #
29
DRAM Address /
Command Copy 1
29
DRAM Address /
Command Copy 2
72 + 18x2
DRAM
Data / strobe
DRAM Cmd