Datasheet

Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
15 of 42
[ Table 5 ] Pin Description
Pin Name Type Pin Description Pin Numbers
SCK Input System Clock Input, positive line 228
SCK
Input System Clock Input, negative line 229
PN[13:0] Output Primary northbound Data, positive lines 22, 25, 28, 31, 34, 37, 40, 48, 51, 54, 57, 60, 63, 66
PN
[13:0] Output Primary northbound Data, negative lines 23, 26, 29, 32, 35, 38, 41, 49, 52, 55, 58, 61, 64, 67
PS[9:0] Input Primary Southbound Data, positive lines 70, 73, 76, 79, 82, 90, 93, 96, 99, 102
PS
[9:0] Input Primary Southbound Data, negative lines 71, 74, 77, 80, 83, 91, 94, 97, 100, 103
SN[13:0] Output Secondary Northbound Data, positive lines
142, 145, 148, 151, 154, 157, 160, 168, 171, 174, 177,
180, 183, 186
SN
[13:0] Output Secondary Northbound Data, negative lines
143, 146, 149, 152, 155, 158, 161, 16, 172, 175, 178,
181, 184, 187
SS[9:0] Input Secondary Southbound Data, positive lines 190, 193, 196, 199, 202, 210, 213, 216, 219, 222
SS
[9:0] Input Secondary Southbound Data, negative lines 191, 194, 197, 200, 203, 211, 214, 217, 220, 223
SCL Input Serial Presence Detect (SPD) Clock Input 120
SDA Input SPD Data Input / Output 119
SA[2:0] Input
SPD Address Inputs, also used to select the DIMM number in
the AMB
118, 239, 240
V
ID
[1:0] NC
Voltage ID : These pins must be unconnected for DDR2 -
based Fully Buffered DIMMs
V
ID
[0] is V
DD
value : OPEN = 1.8 V, GND = 1.5 V ; V
ID
[1] is V
CC
value : OPEN = 1.5V, GND = 1.2V
16, 136
RESET Input AMB reset signal 17
RFU RFU Reserved for Future Use
19, 20, 44, 45, 86, 87, 105, 106, 139, 140, 164, 165,
206, 207, 225, 226
V
CC
PWR AMB Core Power and AMB Channel Interface Power (1.5 Volt) 9, 10, 12, 13, 129, 130, 132, 133
V
DD
PWR DRAM Power and AMB DRAM I/O Power (1.8Volt)
1, 2, 3, 5, 6, 7, 108, 109, 111, 112, 113, 115, 116, 121,
122, 123, 125, 126, 127, 231, 232, 233, 235, 236
V
TT
PWR DRAM Address/Command/Clock Termination Power(V
DD
/2) 15, 117, 135, 237
V
DDSPD
PWR SPD Power 238
V
SS
GND Ground
4, 8, 11, 14, 18, 21, 24, 27, 30, 33, 36, 39, 42, 43, 46,
47, 50, 53, 56, 59, 62, 65, 68, 69, 72, 75, 78, 81, 84, 85,
88, 89, 92, 95, 98, 101, 104, 107, 110, 114, 124, 128,
131, 134, 138, 141, 144, 147, 150, 153, 156, 159, 162,
163, 166, 167, 170, 173, 176, 179, 182, 185, 188, 189,
192, 195, 198, 201, 204, 205, 208, 209, 212, 215, 218,
221, 224, 227, 230, 234
DNU/M_Test DNU
The DNU/M_Test pin provides an external connection R/Cs A-
D for testing the margin of Vref which is produced by a voltage
divider on the module. It is not intended to be used in normal
system operation and must not be connected (DNU) in a sys-
tem. This test pin may have other features on future card de-
signs and if it does, will be included in this specification at that
time.
137