Datasheet

Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
23 of 42
6.0 Electrical Characteristics
[ Table 6 ] Absolute Maximum Ratings
Note : 1. Stresses greater than those Iisted may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
2. DDR2 SDRAMs of FBDIMM should require this specification.
[ Table 7 ] Input DC Operating Conditions
Note : 1. Applies for SMB and SPD bus signals.
2. Applies for AMB CMOS signal RESET
.
3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification.
[ Table 8 ] Timing Parameters
Note : 1. Defined in FB-DIMM Architecture and Protocol Spec
2. Clocks defined as core clocks = 2x SCK input
3. @DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to the DRAMs
4. @ DDR2-667 - measured from latest DQS input AMB TO start of matching data frame at northbound FB-DIMM outputs.
Parameter Symbol MIN MAX Units Note
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.3 1.75 V 1
Voltage on V
CC
pin relative to V
SS
V
CC
-0.3 1.75 V 1
Voltage V
DD
pin relative to V
SS
V
DD
-0.5 2.3 V 1
Voltage on V
TT
pin relative to V
SS
V
TT
-0.5 2.3 V 1
Storage temperature T
STG
-55 100 °C1
DDR2 SDRAM device operating temperature(Ambient) T
CASE
085
°C1,2
85 95
AMB device operating temperature (Ambient) T
CASE
0 110 °C1,2
Parameter Symbol DRAM Units
Average periodic refresh interval tREFI
0 °C ≤ T
CASE
≤ 85°C
7.8
µs
85 °C < T
CASE
≤ 95°C
3.9
µs
Parameter Symbol MIN Nom MAX Units Notes
AMB supply voltage V
CC
1.455 1.50 1.575 V
DDR2 SDRAM supply voltage V
DD
1.7 1.8 1.9 V
Termination voltage V
TT
0.48 x V
DD
0.50 x V
DD
0.52 x V
DD
V
EEPROM supply voltage V
DDSPD
3.0 3.3 3.6 V
SPD Input HIGH (Iogic 1) voltage V
IH
(DC) 2.1 V
DDSPD
V1
SPD Input LOW (logic 0) voltage V
IL
(DC) 0.8 V 1
RESET Input HIGH (logic 1) voltage V
IH
(DC) V 2
RESET Input LOW (logic 0) voltage V
IL
(DC) 0.5 V 1
Leakage Current (RESET) I
L
-90 90 uA 2
Leakage Current (link) I
L
-5 5 uA 3
Parameter Symbol MIN Typ. Max. Units Notes
EI Assertion Pass-Thru Timing tEI Propagatet 4 clks -
EI Deassertion Pass-Thru Timing tEID Bitlock clks 2
EI Assertion Duration tEI 100 clks 1,2
FBD Cmd to DDR Clk out that latches Cmd 8.1 ns 3
FBD Cmd to DDR Write TBD ns
DDR Read to FBD (last DIMM) 5.0 ns 4
Resample Pass-Thru time 1.075 ns
ResynchPass-Thru time 2.075 ns
Bit Lock Interval tBitLock 119 frames 1
Frame Lock Interval tFrameLock 154 frames 1