Datasheet

Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
24 of 42
[ Table 9 ] Power specification parameter and test condition
Symbol Conditions
Power
Supply
Units
Icc_Idle_0 Idle Current, single or last DIMM
L0 state, idle (0 BW)
Primary channel enabled, Secondary Channel Disabled
CKE high. Command and address lines stable.
DRAM clock active.
@1.5V mA
Idd_Idle_0 @1.8V mA
Idd_Idle_0 Total Power W
Icc_Idle_1 Idle Current, first DIMM
L0 state, idle (0 BW)
Primary and Secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
@1.5V mA
Idd_Idle_1 @1.8V mA
Idd_Idle_1 Total Power W
Icc_Active_1 Active Power
L0 state.
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
@1.5V mA
Idd_Active_1 @1.8V mA
Idd_Active_1 Total Power W
Icc_Active_2 Active Power, data pass through
L0 state.
50% DRAM BW to downstream DIMM, 67% read, 33% write.
Primary and Secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
@1.5V mA
Idd_Active_2 @1.8V mA
Idd_Active_2 Total Power W
Idd_Training
(for AMB spec, Not in
SPD)
Training
Primary and Secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
CKE high, Command and address lines stable.
DRAM clock active.
@1.5V mA
Idd_Training
(for AMB spec, Not in
SPD)
@1.8V mA
Idd_Training Total Power W