Datasheet

Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
28 of 42
[ Table 11 ] V
TT
Currents
[ Table 12 ] Reference Clock Input Specifications
Note :
1. 133MHz for PC2-4200 and 166MHz for PC2-5300.
2. Measured with SSC disabled.
3. Measured differentially through the range of 0.175V to 0.525V.
4. The crossing point must meet the absolute and relative crossing point specification simultaneously.
5. V
CROSS_REL_(MIN)
and V
CROSS_REL(MAX)
are derived using the following calculation : Min = 0.5(V
havg
-0.710)+0.250;and Max=0.5(V
havg
-0.710)+0.550,
where Vhavg is the average of V
SCK-HIGHM.
6. Measured with a single-ended input voltage of 1V.
7. Applies to reference clocks SCK and SCK
.
8. Difference between SCK and SCK
input.
9. T1 = [Tdatapath-Tclockpath](excluding PLL loop delays). This parameter is not a direct clock output parameter but in indirectly determines the clock
output parameter T
REF-JITTER.
10. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the reference clock
source, through the TX, to data arrival at the data sampling point in the RX. The clock path is defined from the reference clock source to clock arrival
at the same sampling point. The path delays are caused by copper trace routes. on-chip routing, on-chip buffering, etc. They include the time-of flight
of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth because these de-
lays are modeled by the PLL transfer functions.
11. Direct measurement of phase jitter records over 1016 periods is impractical. It is expected that the jitter will be measured over a smaller, yet statistically
significant, sample size and the total jitter at 10
16
samples extrapolated from an estimate of the sigma of the random jitter components.
12. Measured with SSC enabled on reference clock generator.
13. As measured after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRXTotal - MIN parameters.
Description Symbol Typ MAX Units
Idle current, DDR2 SDRAM device power down ITT1 500 700 mA
Active power, 50% DDR2 SDRAM BW ITT2 500 700 mA
Parameter Symbol
Values
Units Note
MIN MAX
Reference clock frequency @3.2 Gb/s
(nominal 133.33 MHz)
fRefclk-3.2 126.67 133.40 MHz 1.2
Reference clock frequency @4.0 Gb/s
(nominal 166.67 MHz)
fRefclk-4.0 158.33 166.75 MHz 1.2
Rise time, fall time T
SCK-RISE
, T
SCK-FALL
175 700 ps 3
Voltage high V
SCK-HIGH
660 850 mV
Voltage low V
SCK-LOW
-150 mV
Absolute crossing point V
CROSS-ABS
250 550 mV 4
Relative crossing V
CROSS-REL
calculated calculated 4,5
Percent mismatch between rise and
fall times
T
SCK-RISE-FALL-MATCH
-10%
Duty cycle of reference clock T
SCK-DUTYCYCLE
40 60 %
Clock leakage current I
I-CK
-10 10 uA 6,7
Clock input capacitance C
I-CK
0.5 2 pF 7
Clock input capacitance delta C
I_CK(D)
-0.25 0.25 pF 8
Transport delay T1 5 ns 9, 10
Phase jitter sample size NSAMPLE 10
16
Periods 11
Reference clock jitter, filtered T
REF-JITTER
40 ps 12,13
Reference clock deterministic jitter T
REF-DJ
TBD ps