Datasheet

Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
4 of 42
1.0 Features
[ Table 1 ] Ordering Information
Note :
1. “Z” of Part number(11th digit) stands for Lead-Free and RoHS compliant products.
2. “J” of Part number(11th digit) stands for Dual-Die Package based, Lead-Free and RoHS compliant products.
3. The last digit stands for AMB.
[ Table 2 ] Performance range
[ Table 3 ] Address Configuration
Part Number Density Organization Component Composition
Number
of Rank
AMB
Type of
Heat
Spreader
Height
M395T2863QZ4-CE66/F76/E76
1GB 128M x 72 128Mx8(K4T1G084QQ) *9EA 1
IDT C1
Full Module 30.35mm
M395T2863QZ4-CE65 Intel D1
M395T2863QZ4-CE68/F78 IDT L4
M395T2863QZ4-CE63 Montage D3
M395T5663QZ4-CE66/F76/E76
2GB 256M x 72 128Mx8(K4T1G084QQ) *18EA 2
IDT C1
M395T5663QZ4-CE65 Intel D1
M395T5663QZ4-CE68/F78 IDT L4
M395T5663QZ4-CE63 Montage D3
M395T5160QZ4-CE66/F76/E76
4GB 512M x 72
256Mx4(K4T1G044QQ) *36EA 2
IDT C1
M395T5160QZ4-CE65 Intel D1
M395T5160QZ4-CE68 IDT L4
M395T5160QZ4-CE63 Montage D3
M395T5163QZ4-CE68/F78/E78 128Mx8(K4T1G084QQ) *36EA
4
IDT L4
M395T1G60QJ4-CE68/F78 8GB 1G x 72
DDP 512Mx4(K4T2G044QQ)
*36EA
4
IDT L4
F7(DDR2-800) E7(DDR2-800) E6(DDR2-667) Unit
DDR2 DRAM Speed 800 800 667 Mbps
CL-tRCD-tRP 6-6-6 5-5-5 5-5-5 CK
Organization Row Address Column Address Bank Address Auto Precharge
128Mx8(1Gb) based Module A0-A13 A0-A9 BA0-BA2 A10
256Mx4(1Gb) based Module A0-A13 A0-A9, A11 BA0-BA2 A10
- 240pin fully buffered dual in-line memory module (FB-
DIMM)
- 3.2Gb/s, 4.0Gb/s link transfer rate
- 1.8V +/- 0.1V Power Supply for DRAM V
DD
/V
DDQ
- 1.5V +0.075/-0.045V Power Supply for AMB V
CC
- 3.3V +/- 0.3V Power Supply for V
DDSPD
- Buffer Interface with high-speed differential point-to-
point Link at 1.5 volt
- Channel error detection & reporting
- Channel fail over mode support
- Serial presence detect with EEPROM
-8 Banks
-Posted CAS
- Programmable CAS Latency: 3, 4, 5, 6
- Programmable Additive Latency: 0, 1, 2, 3, 4, 5
- Automatic DDR2 DRAM bus and channel calibration
- MBIST and IBIST Test functions
- Hot add-on and Hot Remove Capability
- Transparent mode for DRAM test support