Product manual

Cheetah 4LP FC Product Manual, Rev. A 11
The drive keeps track of the logical block addresses of the data stored in each segment of the cache. If the
cache is enabled (see RCD bit in the
Fibre Channel Interface Manual
), data requested by the host with a read
command is retrieved from the cache, if possible, before any disc access is initiated. Data in contiguous logical
blocks immediately beyond that requested by the Read command can be retrieved and stored in the cache for
immediate transfer to the initiator on subsequent read commands. This is referred to as the prefetch operation.
Since data that is prefetched may replace data already in the cache segment, an initiator can limit the amount
of prefetch data to optimize system performance. The drive never prefetches more sectors than the number
specified in bytes 8 and 9 of Mode page 08h. If the cache is not enabled, 967.5 Kbytes of the buffer are used
as a circular buffer for read/writes, with no prefetch operation and no segmented cache operation.
The following is a simplified description of the prefetch/cache operation:
Case Aread command is received and the first logical block is already in cache:
1. Drive transfers to the initiator the first logical block requested plus all subsequent contiguous logical blocks
that are already in the cache. This data may be in multiple segments.
2. When a requested logical block is reached that is not in any segment, the drive fetches it and any remain-
ing requested logical block addresses from the disc and puts them in a segment of the cache. The drive
transfers the remaining requested logical blocks from the cache to the initiator in accordance with the
“buffer-full” ratio specification given in Mode Select Disconnect/Reconnect parameters, page 02h.
3. The drive prefetches additional logical blocks contiguous to those transferred in step 2 above and stores
them in the segment. The drive stops filling the segment when the maximum prefetch value has been
transferred.
Case Bread command is received and the first logical block address requested is not in any segment of the
cache.
1. The drive fetches the requested logical blocks from the disc and transfers them into a segment, and then
from there to the initiator in accordance with the “buffer-full” ratio specification given in Mode Select Dis-
connect/Reconnect parameters, page 02h.
2. The drive prefetches additional logical blocks contiguous to those transferred in Case A, step 2 above and
stores them in the segment. The drive stops filling the segment when the maximum prefetch value has
been transferred.
During a prefetch, the drive crosses a cylinder boundary to fetch data only if the Discontinuity (DISC) bit is set
to 1 in bit 4 of byte 2 of the Mode Select parameters page 08h. Default is zero for bit 4.
Each cache segment is actually a self-contained circular buffer whose length is an integer number of logical
blocks. The wrap-around capability of the individual segments greatly enhances the cache’s overall perfor-
mance, allowing a wide range of user-selectable configurations. The drive supports operation of any integer
number of segments from 1 to 16. Divide the 967.5 Kbytes in the buffer by the number of segments to get the
segment size. Default is 3 segments.
4.5.1 Caching write data
Write caching is a write operation by the drive that makes use of a drive buffer storage area where the data to
be written to the medium is stored while the drive performs the Write command.
Write caching is enabled independently of read caching. Write caching is disabled by default on ST34501FC
drives. To enable the write cache, use the Write Caching Enable (WCE) bit.
For write caching, the same buffer space and segmentation is used as set up for read functions. When a write
command is issued, the cache is first checked to see if any logical blocks that are to be written are already
stored in the cache from a previous read or write command. If there are, the respective cache segments are
cleared. The new data is cached for subsequent read commands.
If a 10-byte CDB Write command (2Ah) is issued with the data page out (DPO) bit set to 1, no write data is
cached, but the cache segments are still checked and cleared, if need be, for any logical blocks that are being
written.