Product manual

Spinpoint M9TU-USB 3.0 Product Manual REV 1.0
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DISK DRIVE OPERATION
5.2.3 Read/Write IC
The Read/Write IC, shown in Figure 5-2 provides read/write-processing functions for the drive. The
Read/Write IC receives the Read GATE and Write GATE signals, write data, and servo AGC and gates from
the Interface Controller. The Read/Write IC sends decoded read data and the read reference clock. It
receives write data from the Interface Controller.
The 88C10010 which is embedded in 88i1022 is a sampled-data digital PRML channel designed to work
with a disk controller and a read/write preamplifier to provide the signal processing elements required to build
a state of the art high density, high speed disk drive. The 88C10010 implements a noise predictive, PRML
Viterbi read channel (supporting) zone-bit recording,
The read/write channel functions include a time base generator, AGC circuitry, asymmetry correction
circuitry (ASC), analog anti-aliasing low-pass filter, analog to digital converter (ADC), digital FIR filter,
timing recovery circuits, Viterbi detector, sync mark detection, 30/32 rate block code ENDEC, serializer and
de-serializer, and write pre-compensation circuits. Servo functions include servo data detection and PES
demodulation. Additionally the 88C10010 contains specialized circuitry to perform various parametric
measurements on the processed read signal. This allows for implementation of self-tuning and optimization
capability in every drive
built using the 88C10010.
A 12-bit NRZ interface is provided to support high speed data transfers and from the controller.
Programming of the 88C10010 is performed through a serial interface. The serial interface is also used to
read various channel parameters that are computed on the fly.
5.2.3.1 Time Base Generator
The time base generator provides the write frequency and serves as a reference clock to the synchronizer during
non-read mode.
5.2.3.2 Automatic Gain Control
The AGC accepts a differential signal from the pre-amp, and provide constant output amplitude to the analog
filter. It’s capable of accepting signal ranges from 50 mV to 400 mVppd.
5.2.3.3 Asymmetry Correction Circuitry (ASC)
The ASC circuit is designed to correct for amplitude asymmetry introduced by MR heads. The compensation
range of this circuit is +/-30%. This circuit allows optimal bias current to be used independent of the
asymmetry effect.
5.2.3.4 Analog Anti-Aliasing Low Pass Filter
The 5
th
order equal-ripple analog filter provides filtering of the analog signal from AGC before it’s being
converted to digital signal with the ADC. Its main function is to avoid aliasing for the ADC circuit.
5.2.3.5 Analog to Digital Converter (ADC) and FIR
The output of the analog filter is quantified using a 6 bit FLASH ADC. The digitized data is then equalized by
the FIR to the NPV target response for Viterbi detection. The FIR filter consists of 10 independent
programmable taps