Specifications

10
Chipset
The Intel 440BX PCIset includes a Host-PCI bridge integrated with both an optimized
DRAM controller and an Accelerated Graphics Port (A.G.P.) interface. The I/O
subsystem of the 440BX is based on the PIIX4E, which is a highly integrated PCI-
ISA/IDE Accelerator Bridge. This chipset consists of the Intel 82443BX PCI/A.G.P.
controller (PAC) and the Intel 82371EB PCI/ISA IDE Xcelerator (PIIX4E) bridge chip.
Intel 82443BX PCI/A.G.P. controller (PAC)
The PAC provides bus-control signals, address paths, and data paths for transfers
between the processor’s host bus, PCI bus, Accelerated Graphics Port (A.G.P.), and
main memory. The PAC comes in a 492-pin BGA package and features:
• Processor interface control
Support for processor host bus frequencies of 100 MHz or 66 MHz
32-bit addressing
Desktop Optimized GTL+ compliant host bus interface
• Integrated DRAM controller, with support for:
+3.3 V only DIMM DRAM configurations
Up to four double sided DIMMs
Synchronous 100-MHz or 66-MHz SDRAM
SDRAM 64-bit data interface with ECC support
• A.G.P. interface
Complies with the A.G.P. specification (see Section 6.2 for specification
information)
Support for +3.3 V PCI-66, A.G.P.-66/133 devices
Synchronous coupling to the host-bus frequency
• PCI bus interface
Complies with the PCI specification Rev 2.1, +5 V 33 MHz interface
Asynchronous coupling to the host-bus frequency
PCI parity generation support
Data streaming support from PCI-to-DRAM
Support for concurrent host, A.G.P., and PCI transactions to main memory
• Data buffering
DRAM write buffer with read-around-write capability
Dedicated host-to-DRAM, PCI0-to-DRAM, and PCI1/A.G.P.-to-DRAM read buffers
A.G.P. dedicated inbound/outbound FIFOs (133/66 MHz), used for temporary data
storage