Specifications

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SDRAM Precharge Control
When Enabled, all CPU cycles to SDRAM result in an All Banks Precharge Command
on the SDRAM interface.
DRAM Data Integrity Mode
Select Parity or ECC (error-correcting code), according to the type of installed DRAM.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this memory
area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to C7FFFh,
resulting in better video performance. However, if any program writes to this memory
area, a system error may result.
V 8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-originated I/O cycles
to the ISA bus. This delay takes place because the PCI bus is so much faster than the
ISA bus.
These two fields let you add recovery time (in bus clock cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this
area of system memory usually discusses their memory requirements.
Passive Release
When Enabled , CPU to PCI bus accesses are allowed during passive release.
Otherwise, the arbiter only accepts another PCI master access to local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with the PCI specification version 2.1.