Specifications

9
✏NOTE
Processors with 100 MHz front-side bus should be paired only with 100 MHz SDRAM.
Processors with 66 MHz front side bus can be paired with either 66 MHz or 100 MHz
SDRAM.
SDRAM
Synchronous DRAM (SDRAM) improves memory performance through memory access
that is synchronous with the memory clock. This simplifies the timing design and
increases memory speed because all timings are dependent on the number of memory
clock cycles.
✏NOTE
All memory components and DIMMs used with this motherboard must comply with the
PC SDRAM specifications. These include the PC SDRAM Specification (memory
component specific), the PC Un-buffered DIMM Specification, and the PC Serial
Presence Detect Specification. You can access these documents through the Internet
at http://www.intel.com/design/pcisets/memory/
ECC Memory
ECC memory detects multiple-bit errors and corrects single-bit errors. When ECC
memory is installed, the BIOS supports both ECC and non-ECC mode. ECC mode is
enabled in the Setup program. The BIOS automatically detects if ECC memory is
installed and provides the Setup option for selecting ECC mode. If any non-ECC
memory is installed, the Setup option for ECC configuration does not appear and ECC
operation is not available.
The following table describes the effect of using Setup to put each memory type in each
supported mode. Whenever ECC mode is selected in Setup, some performance loss
occurs.
Cache Memory
The Intel microprocessors include 32 KB (16K/16K) non-blocking level one cache and
up to 1 MB unified, non-blocking level two cache on the substrate in the Single Edge
Connector (S.E.C.) cartridge. The size of level two cache varies between the Intel

Celeron

, Pentium

II and Pentium

III processors, it could be 0KB, 128KB, 256KB or
512 KB.