User's Manual
Table Of Contents
- User Manual of SRM100A(Rev1.0)
- 1. Introduction
- 2. Hardware Architecture:
- 2.1 Main Chipset Information
- 2.2 Circuit Block Diagram
- Figure 1-1 SRM100A block diagram and System Interface
- 3. Operational Description
- 3.1 Features
- 3.2 Time base of the RF frequency
- 3.3 Transmission
- 3.4 Receiver
- 3.5 Product Details
- 3.6 Output Power tolerance
- 3.7 SRM100A Category of signal
-BLE
In 2.4GHz transmission, TX IQ signal is inputted through DAC in IC and transmitted through amplification stage
t
hrough TX carrier frequency.
3.4 R
eceiver
-
SIGFOX
The Rx path is able to receive sub-1GHz signal and the noise amplifier is built in the inside of the chip, it
amplifies the received signal by the low noise amplifier according to the receiving intensity, and the amplified
signal is converted into the digital signal through the ADC, Packets will be interpreted.
-BLE
The transceiver IC is isolated to prevent unwanted noise emission by the internal low noise amplifier stage, and
t
he RF signal is converted and demodulated into RX IQ signal through the intermediate frequency, low pass
filter, and input to the baseband processing section.
3.5 P
roduct Details
-SIGFOX
> Data Modulation
TX : D
BPSK
RX : 2GFSK
> Frequency :
Sigfox zone Uplink/TX (MHz)
RC2 902.1375 ~ 904.6625
RC4 920.7375 ~ 923.2625
-
BLE
> Data Modulation : GFSK
> Frequency : 2402-2480MHz
3.6 Conducted output Power tolerance
-SIGFOX Output power : 23.5dBm (tolerance: +/- 2dBm)
-BLE Output power : 1.0dBm (toleranc
e: +/- 2dBm)
Version 1.0 SEONG JI page 3 of 6