Service manual
•
Read
For
plane read data from the VRAM, data to
be
read
by the
CPU
are arranged in accordance with the
direction
of
the read format register
(RF).
* Logic circuit
11"'0
-1
~".n.
•.
t.
11
)
\/eo
-1
t
Pl
IMII.IJJ,IV!
Read
data from the VRAM and write data from the
CPU
are subjected to logical operation
(OR,
XOR,
RESET,
etc.) and its result is used
for
the write data.
VRAM
acee
..
timing
1)
MZ-700 mode
See
separate page
for
display timing chart.
The
VRAM
is
configured in the following manner in
this instance.
VA
vc
(option)
$0000
Not used
$2000
Not
used
CG
area
$3000
TEXT area
ATB area
$3FFF
16
MZ-800
As the
PCG
method
is
adopted for the MZ-700 mode,
the text and ATB areas are
actually mapped to $0000
-
$OFFF.
So, the VRAM address
has
the following
relation
with the display character position.
1 2 3
40
:1::
1
0001
1-1
======t=a
I I I I I
I I I I I I
I I I I I I
251
03CO
I I I
-_-_~~~~
2)
MZ-800 mode
As
the bit map method is used for the MZ-800 mode,
it
is possible to four screens
of
320
x
200
dots and
two
screens (maximum)
of
640'x
200
data.
The
cycle steal method is used
for
this mode.
i)
320
x
200
dots
See
separate page
for
the timing chart
duing
display and
CPU
read timing.
What
i.
p.eudo
cycle steal
With the MZ-800, the pseudo cycle steal method is
adopted
for
VRAM accessing.
LOAO~
u
x:~~.
===:x
OISP.
addr
..
s X
cpu
address X
OISP.
add
re
..
I--
OISP.
clcle I
CPU
clcle I
OISP.
clcle
As shown in the figure, a next display data fetch and
CPU
accessing are multiplexed during a display period.
Because accessing
of
the VRAM while characters are on
display causes the screen to blink with the MZ-700
mode,
it
awaits
for
blinking to complete before
acces-
sing
of
the VRAM. But, with the cycle steal method it
enhances faster screen processing
as
it
enables to
access the
VRAM during a display period. Because
it
is
not a complete cycle steal with the MZ-800 but timing is
taken using a
wait
in order to synchronize with the
CPU
cycle
for
accessing from the
CPU,
it
is therefore called
"pseudo cycle steal
H
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