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DDR3 UDIMM w/o ECC

Product Specification

Features

• DDR3 functionality and operations supported as defined in the component data sheet

• 240pin, unbuffered dual in-line memory module (UDIMM)

• Fast data transfer rates: PC3-8500, PC3-10600, PC3-12800

• Single or Dual rank

• 1GB(128 Meg x 64), 2GB (256 Meg x 64), 4GB (512Meg x 64)

• V

= V

DDQ

= 1.5V ±0.075V

• V

DDSPD

= 3.0V to 3.6V

• Reset pin for improved system stability

• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)

• Fly-by topology

• Terminated control, command, and address bus

• Adjustable data-output drive strength

• Serial presence-detect (SPD) EEPROM

• Gold edge contacts

• Pb-free

Rev. 14 Dec. 2011

Summary of content (6 pages)

PAGE 1
DDR3 UDIMM w/o ECC Product Specification Features • DDR3 functionality and operations supported as defined in the component data sheet • 240pin, unbuffered dual in-line memory module (UDIMM) • Fast data transfer rates: PC3-8500, PC3-10600, PC3-12800 • Single or Dual rank • 1GB(128 Meg x 64), 2GB (256 Meg x 64), 4GB (512Meg x 64) • V DD = V DDQ = 1.5V ±0.075V • V DDSPD = 3.0V to 3.
PAGE 2
DDR3 UDIMM w/o ECC Product Specification Module Specification Bandwidth Data Rate Timing (tCL-tRCD-tRP) PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-12800 DDR3-1600 9-9-9 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-12800 DDR3-1600 11-11-11 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-12800 DDR3-1600 11-11-11 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-8500 DDR3-1066 7-7-7
PAGE 3
DDR3 UDIMM w/o ECC Product Specification Pin Assignments 240-Pin UDIMM Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VREFDQ VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS NC NC CKE0 VDD BA2 NC VDD A11 A
PAGE 4
DDR3 UDIMM w/o ECC Product Specification Pin Description Symbol Type A0–A14 Input BA0–BA2 Input Description Address inputs: Provide the row address for ACTIVE commands and the column address and auto precharge bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
PAGE 5
DDR3 UDIMM w/o ECC Product Specification Simplified Mechanical Drawing(x8 1Rank) Note: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note: 2. The dimensional diagram is for reference only. 5 Rev. 14 Dec.
PAGE 6
DDR3 UDIMM w/o ECC Product Specification Simplified Mechanical Drawing(x8 2Ranks) Note: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note: 2. The dimensional diagram is for reference only. 6 Rev. 14 Dec.