MSM80C154S MSM83C154S MSM85C154HVS USER'S MANUAL
Copyright 1988, OKI ELECTRIC INDUSTRY COMPANY, LTD. OKI makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. OKI retains the right to make changes to these specifications at any time, without notice.
CONTENTS 1. INTRODUCTION 1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline .................................. 3 1.2 MSM80C154S/MSM83C154S Features ............................................................. 5 1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS ........... 7 2. SYSTEM CONFIGURATION 2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols .................... 11 2.2 MSM80C154S/MSM83C154S Pin Layout ........................................................12 2.2.
3. CONTROL 3.1 Oscillators [XTAL1 .2] .......................................................................................43 3.2 CPU Resetting ..................................................................................................45 3.2.1 Outline .......................................................................................................45 3.2.2 Reset Schmitt trigger circuit .......................................................................50 3.2.
4.5.2.5.7 Caution about use of timer counters 0 and 1 .................................. 90 4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software power down mode........................................................................... 91 4.5.3 Timer/counter 2 .........................................................................................92 4.5.3.1 Outline ...................................................................................................92 4.5.3.
4.6.4.2 Multi-processor systems ......................................................................128 4.7 Interrupt .............................................................................................................129 4.7.1 Outline .....................................................................................................129 4.7.2 Interrupt enable register (IE) .................................................................... 131 4.7.3 Interrupt priority register (IP) ...........
5.7 High Impedance Input Port Setting of Each Quasi-bidirectional Port 1, 2, and 3 ...............................................................................................207 5.8 100 kW Pull-Up Resistance Setting for Quasi-bidirectional Input Ports 1, 2, and 3 .............................................................................................207 5.9 Precautions When Driving External Transistors by Quasi-bidirectional Port Output Signals ......................................................
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MSM80C154S/83C154S/85C154HVS 2
INTRODUCTION 1. INTRODUCTION 1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline MSM80C154S/MSM83C154S/MSM85C154HVS are single-chip 8-bit fully static microcontrollers featuring high performance and low power consumption. All MSM80C31F /MSM80C51F instructions and functions have been retained. Apart from being without the internal program memory (ROM), MSM80C154S is identical to MSM83C154S.
MSM80C154S/83C154S/85C154HVS execution from the next address after the stop address where CPU power down mode was activated. Each of the quasi-bidirectional ports 1, 2, and 3 can be set independently as high impedance input ports. And the 10 kW pull-up resistance for these input ports can be isolated from the power supply (VCC), leaving only the 100 kW pull-up resistance and thereby enabling the quasi-bidirectional ports to be driven by devices with low drive capacity.
INTRODUCTION 1.
MSM80C154S/83C154S/85C154HVS • Timer/counters (three 16-bit timer/counters) (1) 8-bit timer with 5-bit prescalar (2) 16-bit timer (3) 8-bit timer with 8-bit auto-reloader (4) 8-bit separate timer (5) 16-bit timer with 16-bit auto-reloader (6) 16-bit capture timer (7) 16-bit baud rate generator timer (8) 32-bit timer • Wide operating temperature range –40 to +85°C • Wide operating voltage range (1) When operating: VCC=+2.
INTRODUCTION 1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS In addition to the basic operations of MSM80C31F/MSM80C51F, the MSM80C154S/ MSM83C154S/MSM85C154HVS devices also include the following functions.
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SYSTEM CONFIGURATION 2. SYSTEM CONFIGURATION 2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 XTAL1 XTAL2 RESET ADDRESS LATCH ENABLE PROGRAM STORE ENABLE RESET P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 ALE PSEN P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 EA CPU MEMORY SEPARATE PORT 0 (BUS PORT) +5(V) VCC 0(V) VSS P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.
MSM80C154S/83C154S/85C154HVS 2.2 MSM80C154S/MSM83C154S pin layouts MSM80C154SRS/MSM83C154SRS (Top View) 40 Pin Plastic DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MSM80C154SRS/MSM83C154SRS P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/HPDI P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P1.
SYSTEM CONFIGURATION NC 2 1 44 43 42 41 40 P0.3 P1.0/T2 3 P0.2 P1.1/T2EX 4 P0.1 P1.2 5 P0.0 P1.3 6 39 P0.4 MSM80C154SJS/MSM83C154SJS P1.5 7 VCC P1.4 MSM80C154SJS/MSM83C154SJS (Top View) 44 Pin Plastic QFJ P1.6 8 P1.7 9 RESET 10 P3.0/RXD 11 NC 12 P3.1/TXD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/T1/HPDI 17 38 P0.5 37 P0.6 36 P0.7 35 EA 34 NC 33 ALE 32 PSEN 31 P2.7 30 P2.6 29 P2.5 P2.4 P2.3 P2.2 P2.1 NC P2.0 VSS XTAL1 XTAL2 P3.7/RD P3.
MSM80C154S/83C154S/85C154HVS Applicable Packages 40-Pin Plastic DIP (DIP40-P-600-2.54) MSM80C154S RS MSM83C154S-XXX RS 44-Pin Plastic QFJ (QFJ44-P-S650-1.27) MSM80C154S JS MSM83C154S-XXX JS 44-Pin Plastic QFP (DFP44-P-910-0.80-2K) MSM80C154S GS-2K MSM83C154S-XXX GS-2K 44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K) MSM80C154S TS-K MSM83C154S-XXX TS-K 40-Pin Ceramic Piggy Back (ADIP40-C-600-2.
SYSTEM CONFIGURATION 2.2.1 MSM80C154S/MSM83C154S external dimensions MSM80C154SRS/MSM83C154SRS 40-pin Plastic DIP (DIP40-P-600-2.54) MSM80C154SGS/MSM83C154SGS 44-Pin Plastic QFP (QFP44-P-910-0.80-2K) MSM80C154SJS/MSM83C154SJS 44-Pin Plastic QFJ (QFJ44-P-S650-1.
MSM80C154S/83C154S/85C154HVS MSM80C154STS/MSM83C154STS 44-Pin Plastic TQFP (TQFP44-P-1010-0.
SYSTEM CONFIGURATION 2.2.2 MSM85C154HVS pin layout and external dimensions M85C154H OKI JAPAN XXXX 2764/27128 Pin 1 for 2764, 27128 * The MSM85C154HVS pin layout of bottom side is the same as the pin layout for MSM83C154SRS. * The 27C64/128 device should be used for EPROM. 40-Pin Ceramic Piggy Back (ADIP40-C-600-2.
ALE EA RESET P3.7 PORT 3 P3.0 PCLL PCH IR PCL AIR C-ROM TL2 TH2 R/W AMP RCAP 2H 256WORD ×8bit ACC TR2 TR1 TIMER/ COUNTER 2 PORT 1 P1.7 PLA SP T2CON P1.
XTAL2 ALE EA RESET PCHL SP SPECIAL FUNCTION REGISTER ADDRESS DECODER PLA IR PCL AIR TL2 TH2 R/W AMP RCAP 2H 256WORD ×8bit ACC TR2 TR1 TIMER/ COUNTER 2 RCAP 2L TH1 TL1 TH0 TL0 TMOD TIMER/COUNTER 0&1 TCON RAMDP PSW IE IP INTERRUPT ALU SBUF (T) SBUF (R) SERIAL IO BR SCON SYSTEM CONFIGURATION P3.7 PORT 3 P3.0 SENSE AMP SIGNAL C-ROM PORT 1 P1.7 DPL R/W PCLL PCH T2CON P1.
ALE EA RESET D0 ... D7 P3.7 PORT 3 P3.0 IR PCL AIR TL2 TH2 R/W AMP RCAP 2H 256WORD ×8bit ACC TR2 TR1 TIMER/ COUNTER 2 PORT 1 P1.7 SP C-ROM T2CON P1.
SYSTEM CONFIGURATION 2.6 Timing and Control 2.6.1 Outline of MSM80C154S/MSM83C154S timing The MSM80C154S/MSM83C154S devices are both equipped with a built-in oscillation inverter (see Figure 2-8) for use in the generation of clock pulses by external crystal or ceramic resonator. These clock pulses are passed to the timing counter and control circuits where the basic timing and control signals required for internal control purposes are generated.
1 0 1 0 1 0 1 0 1 0 1 0 XTAL1 ALE PSEN RD/WR PORT–0 PORT–2 STEP CYCLE PCH S1 S4 PCH S3 PCL S2 M1 S1 PCH S6 PCL S5 S4 PCH S3 PCL S2 M1 S6 DPL & Rr S5 S1 S3 ACC & RAM S2 M2 S4 S1 PCH S6 PCL S5 S4 PCH S3 PCL S2 M1 S6 PCL S5 MSM80C154S/83C154S/85C154HVS Figure 2-9 MSM80C154S/MSM83C154S fundamental timing 1 0 1 0 CPU←PORT PORT←CPU 22 PC+1 TM+1 PC+1 Instruction excecution Instruction decoding PORT OLD DATA DATA STABLE PC+1 TM+1 Instruction decodin
SYSTEM CONFIGURATION 2.6.2 Major synchronizing signals (1) ALE (Address Latch Enable) The ALE signal is used as a clock signal where the address signals 0 thru 7 output from CPU port 0 can be latched externally when external program or external data memory (RAM) is used. Although two ALE signal outputs are obtained in a single machine cycle during normal operations, no output is obtained during output of the RD/WR signal when an external memory instruction (MOVX...... ) is executed.
MSM80C154S/83C154S/85C154HVS 2.6.
SYSTEM CONFIGURATION (3) MOVX @Rr, A M1 S1 S2 XTAL1 1 0 ALE 1 0 PSEN 1 0 WR 1 0 PORT–0 1 0 PORT–2 1 PCH OUT 0 S3 M2 S4 S5 S6 S1 S2 S3 S4 S5 S6 INST IN S1 INST IN PCL OUT Rr OUT PCH OUT ACC DATA OUT PCL OUT PORT 2 LATCH DATA OUT PCH OUT Figure 2-12 MSM80C154S MOVX @Rr, A execution (4) MOVX A, @DPTR M1 S1 S2 XTAL1 1 0 ALE 1 0 PSEN 1 0 RD 1 0 PORT–0 1 0 PORT–2 1 PCH OUT 0 S3 M2 S4 S5 S6 INST IN PCL OUT DPL OUT PCH OUT S1 S2 S3 S4 RAM DATA IN EXT RAM DA
MSM80C154S/83C154S/85C154HVS (5) MOVX @DPTR, A M1 S1 S2 XTAL1 1 0 ALE 1 0 PSEN 1 0 WR 1 0 PORT–0 1 0 PORT–2 1 PCH OUT 0 S3 M2 S4 S5 S6 S1 S2 S3 S4 S5 S6 INST IN S1 INST IN PCL OUT DPL OUT ACC DATA OUT PCH OUT PCL OUT DPH OUT PCH OUT Figure 2-14 MSM80C154S MOVX @DPTR, A execution (6) MOV direct, PORT [0, 1, 2, 3] execution M1 S1 XTAL1 1 0 ALE 1 0 PSEN 1 0 S2 S3 M2 S4 S5 S6 S1 S2 S3 S4 S5 PORT 0,1,2,3 1 PIN DATA 0 CPU DATA SAMPLED 1 0 PIN DATA STABLE Figure
SYSTEM CONFIGURATION 2.6.
MSM80C154S/83C154S/85C154HVS (3) MOVX A, @DPTR M1 S1 S2 S3 M2 S4 S5 XTAL1 1 0 ALE 1 0 PSEN 1 0 RD 1 0 PORT–0 1 0 PORT–2 1 PORT 2 LATCH DATA OUT 0 S6 S1 S3 S4 S5 RAM DATA IN EXT RAM DATA DPL OUT PORT 0 LATCH DATA S2 S6 S1 FLOATING PORT 2 LATCH DATA OUT DPH OUT Figure 2-18 MSM83C154S MOVX A, @DPTR execution (4) MOVX @DPTR, A M1 S1 S2 S3 M2 S4 S5 XTAL1 1 0 ALE 1 0 PSEN 1 0 WR 1 0 PORT–0 1 0 PORT–2 1 PORT 2 LATCH DATA OUT 0 PORT 0 LATCH DATA S6 DPL OUT S1 S2
SYSTEM CONFIGURATION (5) MOV direct, PORT [0, 1, 2, 3] execution M1 S1 XTAL1 1 0 ALE 1 0 PSEN 1 0 PORT 0,1,2,3 1 PIN DATA 0 CPU DATA SAMPLED 1 0 S2 S3 M2 S4 S5 S6 S1 S2 S3 S4 S5 PIN DATA STABLE Figure 2-20 MSM83C154S MOV direct, PORT[0, 1, 2, 3] execution 29 S6 S1
MSM80C154S/83C154S/85C154HVS 2.7 Instruction Register (IR) and Instruction Decoder (PLA) MSM80C154S/MSM83C154S operations are based on an instruction code address method. Hence, in addition to the instruction code instruction register (IR) and instruction decoder (PLA), these devices also include an instruction register (AIR) and register manipulation decoder (PLA) for data addresses and bit addresses. Operation codes are passed to the IR, and data and bit addresses are passed to the AIR.
SYSTEM CONFIGURATION 2.8 Arithmetic Operation Section (1) Outline The MSM80C154S/MSM83C154S arithmetic operation section consists of (1) an arithmetic operation instruction decoder, and (2) an arithmetic and logic unit [ALU]. (2) Arithmetic operation instruction decoder: Arithmetic operation instructions are passed to the instruction register (IR) and then to the PLA where they are converted into control signals.
MSM80C154S/83C154S/85C154HVS 2.9 Program Counter The MSM80C154S/MSM83C154S program counter has a 16-bit configuration PC0 thru PC15, as shown in Figure 2-23.
SYSTEM CONFIGURATION 2.10 Program Memory and External Data Memory 2.10.1 MSM80C154S/MSM83C154S program area and external ROM connections Since MSM80C154S/MSM83C154S are equipped with a 16-bit program counter, these devices can execute programs of up to 64K bytes (including both internal and external programs). Since the MSM80C154S is not equipped with an internal program ROM, however, only external instructions are executed.
Q0 A0 P0.1 D1 Q1 A1 P0.2 D2 Q2 A2 P0.3 D3 Q3 A3 P0.4 D4 Q4 A4 P0.5 D5 Q5 A5 P0.6 D6 Q6 A6 P0.7 D7 Q7 A7 ALE LATCH P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P2.6 A14 P2.7 A15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 ROM 64kW × 8BIT CS PSEN OUTPUT ENABLE MSM80C154S/83C154S/85C154HVS D0 MSM74HC373 MSM80C154S/MSM83C154S Figure 2-25 MSM80C154S/MSM83C154S external ROM connection diagram 34 P0.
SYSTEM CONFIGURATION 2.10.2 Procedures and circuit connections used when external data memory (RAM) is accessed by data pointer (DPTR) The MSM80C154S/MSM83C154S can be connected to an external 64K word × 8-bit data memory (RAM) when accessing the memory by data pointer (DPTR). The data pointer (DPTR) consists of DPL and DPH registers. The DPL register contents serve as addresses 0 thru 7 of the external data memory, and the DPH register contents serve as addresses 8 thru 15.
Q0 I/O 0 A0 P0.1 D1 Q1 A1 P0.2 D2 Q2 A2 P0.3 D3 Q3 A3 P0.4 D4 Q4 A4 P0.5 D5 Q5 A5 P0.6 D6 Q6 A6 P0.7 D7 Q7 A7 ALE LATCH P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P2.6 A14 P2.7 A15 WR R/W RD CS 1 2 3 4 ROM 64kW × 8BIT 5 6 7 MSM80C154S/83C154S/85C154HVS D0 MSM74HC373 MSM80C154S/MSM83C154S Figure 2-26 Connection circuit for external data memory addressed by DPTR 36 P0.
1 0 1 0 1 PCL 0 1 0 1 0 XTAL1 ALE PSEN PORT–0 PORT–2 WR 37 1 0 1 0 1 0 1 PCL 0 1 0 1 0 XTAL1 ALE PSEN PORT–0 PORT–2 RD S2 M1 S3 S4 S2 S3 M1 S4 PCH PCH PCL PCH INSTRUCTION IN S1 PCL INSTRUCTION IN S1 PCH S6 1 0 S6 S1 PCH S6 PCL S5 S1 PCH S6 PCL S5 S4 M1 PCH S4 PCH S3 PCL S2 M1 S3 PCL S2 S6 S1 S6 Figure 2-27 DPTR external data memory access timing S1 DPH S2 M2 S3 S4 S4 S1 PCH S6 PCL S5 S1 PCH S6 PCL S5 RAM DATA IN DPH MOVX A,
MSM80C154S/83C154S/85C154HVS 2.10.3 Procedures and circuit connections used when external data memory (RAM) is accessed by registers R0 and R1 The MSM80C154S/MSM83C154S can be connected to an external 256 word ¥ 8-bit data memory (RAM) when addressing the memory according to the contents of registers R0 and R1 in the internal data memory (RAM).
D2 D3 D4 P0.2 P0.3 P0.4 CS RD D1 P0.1 WR LATCH ALE D0 MSM74HC373 P0.0 R/W A7 D7 P0.7 Q7 A5 A6 Q6 D6 P0.6 Q5 D5 P0.
1 0 1 0 1 PCL 0 1 0 1 0 XTAL1 ALE PSEN PORT–0 PORT–2 WR 40 1 0 1 0 1 0 1 PCL 0 1 0 1 0 XTAL1 ALE PSEN PORT–0 PORT–2 RD S2 M1 S3 S4 S2 S3 M1 S4 PCH PCH PCL PCH INSTRUCTION IN S1 PCL INSTRUCTION IN S1 PCH S6 1 0 S6 S1 PCH S6 PCL S5 S1 PCH S6 PCL S5 S4 M1 PCH S4 PCH S3 PCL S2 M1 S3 PCL S2 S5 S5 S4 S1 S2 M2 S4 S1 PCH S6 PCL S5 S1 PCH S6 PCL S5 RAM DATA IN S3 PORT 2 LATCH DATA S6 MOVX A, @Rr Rr M2 S3 ACC DATA S2 PORT 2 LATCH
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CONTROL 3. CONTROL 3.1 Oscillators: XTAL1 XTAL2 An oscillator is formed by connecting a crystal or ceramic resonator between the XTAL1 and XTAL2 pins of the MSM80C154S/MSM83C154S devices. If an external clock is applied to XTAL1, the input should be at 50% duty and C-MOS level. IDLE MODE CPU CONTROL CLOCK PD & HPD MODE C * C TIMER, S I/O & INTERRUPT XTAL1 XTAL 1MΩ XTAL2 * MSM80C154S/MSM83C154S * The capacity of the compensating capacitor depends on the crystal resonator.
MSM80C154S/83C154S/85C154HVS IDLE MODE CPU CONTROL CLOCK PD & HPD MODE TIMER, S I/O & INTERRUPT C XTAL1 * C XTAL2 1MΩ * MSM80C154S/MSM83C154S * The capacity of the compensating capacitor depends on the ceramic resonator. * The XTAL1·2 frequency depends on VCC.
CONTROL 3.2 CPU Resetting 3.2.1 Outline If a reset signal (kept at “1” level for at least 1µsec) is applied to the RESET pin when the correct voltage (in respect to the various specifications) is applied to the MSM80C154S/ MSM83C154S VCC pin, a reset signal is stored in the CPU even if the XTAL1·2 oscillators have been stopped. The internally stored reset signal is used in direct initialization (setting to “1”) of ports 0, 1, 2, and 3.
46 PORT DATA PORT DATA 1 0 1 0 1 0 1 0 1 0 PORT 0 PORT 1 PORT 2 PORT 3 RESET RESET EXCECUTE 1 0 CPU RESET 1 CONTROL 0 PORT DATA 1 0 PSEN PORT DATA 1 0 S3 ALE S2 1 0 S1 XTAL1 S6 S4 M1 or M2 S5 S6 S1 S2 S3 M1 S6 FLOATING S5 S1 S2 S3 S4 S5 CPU RESET EXCECUTE CYCLE PORT DATA = 1 PORT DATA = 1 PORT DATA = 1 S4 M2 S6 S1 S2 S3 M1 S4 S5 S6 MSM80C154S/83C154S/85C154HVS Figure 3-5 Reset execution time chart (internal ROM mode)
1 0 1 0 1 0 1 0 1 0 ALE PSEN PORT 0 PORT 2 RESET 47 S4 PORT DATA PORT DATA 1 0 1 0 PORT 1 PORT 3 PCH S3 PCL S2 1 0 PCH S1 RESET EXCECUTE CPU RESET 1 CONTROL 0 1 0 XTAL1 S6 M1 or M2 S5 S6 S1 S2 S3 M1 S6 FLOATING S5 S1 S2 S3 S4 S5 PORT DATA = 1 PORT DATA = 1 CPU RESET EXCECUTE CYCLE PORT DATA = 1 S4 M2 S6 S1 S2 S3 M1 S4 S5 S6 CONTROL Figure 3-6 Reset execution time chart (external ROM mode)
S6 48 RESET EXCECUTE 1 0 CPU RESET EXCECUTE CYCLE 1 0 RESET CPU RESET 1 CONTROL 0 PORT DATA = 1 1 0 PORT 3 S1 PORT DATA = 1 FLOATING S5 1 0 S4 PORT 2 S3 PORT DATA = 1 S2 1 0 S1 PORT 1 S6 1 0 S5 PORT 0 S4 1 0 S3 PSEN S2 1 0 1 0 S1 M1 ALE XTAL1 S6 M1 S2 S3 M2 S4 S5 S6 S2 S3 S4 EXCECUTE CYCLE S1 M1 S5 S6 MSM80C154S/83C154S/85C154HVS Figure 3-7 Reset release time chart (internal ROM mode)
1 0 1 0 1 0 1 0 PSEN PORT 0 PORT 2 RESET 49 S6 S1 S2 S3 S6 FLOATING S5 S1 PORT DATA = 1 S4 PORT DATA = 1 1 0 PORT 3 CPU RESET EXCECUTE CYCLE S5 PORT DATA = 1 S4 1 0 S3 PORT 1 S2 1 0 S1 M1 RESET EXCECUTE CPU RESET 1 CONTROL 0 1 0 1 0 ALE XTAL1 S6 M1 S2 S3 M2 S4 S6 PCL S5 S3 PCL S2 PCH S4 EXCECUTE CYCLE PCH S1 M1 S6 PCH PCL S5 CONTROL Figure 3-8 Reset release time chart (external ROM mode)
MSM80C154S/83C154S/85C154HVS 3.2.2 Reset Schmitt trigger circuit The Schmitt trigger circuit connected to the RESET pin shown in the MSM80C154S/ MSM83C154S reset circuit block diagram in Figure 3-4 operates in the following way when the VCC power supply voltage is +5V.
CONTROL 3.2.3 CPU internal status by reset When a reset signal is applied to the CPU with normal voltage applied to the MSM80C154S/ MSM83C154S VCC power supply pin, ports 0, 1, 2, and 3 are set to “1” (input mode) even if XTAL1·2 oscillation has been stopped. The output status of the ALE and PSEN pins also becomes “1”. The CPU is then reset after normal XTAL1·2 oscillation has resumed. The internal CPU status when the CPU is reset is shown in Table 3-1.
MSM80C154S/83C154S/85C154HVS 3.3 EA (CPU Memory Separate) 3.3.1 Outline The function of the EA pin is to determine whether a CPU internal program memory (ROM) instruction or an external program instruction is to be executed. (1) Internal ROM mode If the EA pin is connected to VCC and a “1” reset signal is applied to the RESET pin to reset the CPU, an internal program memory (ROM) is executed from address 0.
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INTERNAL SPECIFICATIONS 4. INTERNAL SPECIFICATIONS 4.1 Internal Data Memory (RAM) and Special Function Registers 4.1.1 Outline MSM80C154S/MSM83C154S operation is based on an instruction code address method where operations are specified in an instruction code (OP) section, and the data memory (RAM) and special function registers (ACC, B, TCON, P0........ ) are specified directly by part of the instruction code and the second or third byte of data following that instruction code.
MSM80C154S/83C154S/85C154HVS IOCON 0FFH~0F8H 248 (0F8H) B 0F7H~0F0H 240 (0F0H) REGISTER INDIRECT ADDRESSING USER DATA RAM ACC 0E7H~0E0H 224 (0E0H) PSW 0D7H~0D0H 208 (0D0H) TH2 205 (0CDH) TL2 204 (0CCH) RCAP2H 203 (0CBH) RCAP2L 202 (0CAH) T2CON 0CFH~0C8H 200 (0C8H) IP 0BFH~0B8H 184 (0B8H) P3 0B7H~0B0H 176 (0B0H) IE 0AFH~0A8H 168 (0A8H) P2 0A7H~0A0H 160 (0A0H) SPECIAL FUNCTION REGISTERS HEX OFF SBUF 9FH~98H P1 97H~90H 152 (98H) 144 (90H) TH1 141 (8DH) TH0 140 (8C
INTERNAL SPECIFICATIONS 4.2 Internal Data Memory (RAM) 4.2.1 Internal data memory (RAM) The storage capacity of the MSM80C154S/MSM83C154S data memory is 256 words ¥ 8 bits. The layout diagram is shown in Figure 4-2. The data memory can be accessed (R/W) in four different ways - direct register designation, indirect register designation, data addressing, and bit addressing. Four banks of registers group (R0 thru R7 ¥ 4) exist within the data memory address range from 00 to 1FH.
MSM80C154S/83C154S/85C154HVS 128 127 30H 2FH 7F 7E 7D 7C 7B 7A 79 78 48 47 2EH 77 76 75 74 73 72 71 70 46 2DH 6F 6E 6D 6C 6B 6A 69 68 45 2CH 67 66 65 64 63 62 61 60 44 2BH 5F 5E 5D 5C 5B 5A 59 58 43 2AH 57 56 55 54 53 52 51 50 42 29H 4F 4E 4D 4C 4B 4A 49 48 41 28H 47 46 45 44 43 42 41 40 40 27H 3F 3E 3D 3C 3B 3A 39 38 39 26H 37 36 35 34 33 32 31 30 38 25H 2F 2E 2D 2C 2B 2A 29 28 37 24H 27 26 25 24 23 22 21 20 36 23H 1F 1E 1D 1C 1B 1A 19 18 35 22H 17 16 15 14 13 12 1
INTERNAL SPECIFICATIONS 4.2.2 Internal data memory registers R0 thru R7 Four banks of registers group exist in the data memory (RAM) between memory addresses 00 thru 1FH. Banks are specified by RS0 and RS1 bit combinations within the program status word (PSW). Note that the register area R0 thru R7 can also be used as normal data memory. The PSW table is shown in Table 4-1, and the data memory register bank layout in Figure 43.
MSM80C154S/83C154S/85C154HVS 4.2.3 Stack The stack data save (storage) area is in the internal data memory (RAM), and is specified by stack pointer (SP 81H). Although 07H data is automatically set in the stack pointer when the CPU is reset, any desired data can be set by software to enable the data memory to be used as stack from any address. Two bytes of data memory are used when the stack is used by interrupt or CALL instruction, and a single byte of data memory is used when the PUSH instruction is used.
INTERNAL SPECIFICATIONS 4.3 lnternal Data Memory (RAM) Operating Procedures 4.3.1 Internal data memory indirect addressing Operation of the internal data memory indirect increment instruction is described here as an example. This instruction (INC @Rr) is a 1-byte 1-machine cycle instruction (see Figure 44). The indirect address register is specified by instruction code bit 0 data r where r denotes either register 0 or 1 in the register group specified by PSW RS0 and RS1 bank data.
MSM80C154S/83C154S/85C154HVS 4.3.2 Internal data memory register R0 thru R7 designation Operation of the internal data memory register decrement instruction is described here as an example. This instruction (DEC Rr) is a 1-byte 1-machine cycle instruction (see Figure 4-5). Register R0 thru R7 is specified by r0, r1, and r2 data of instruction code bit 0, 1, and 2. The r0, r1, and r2 data is represented in binary code, r0 being the LSB, and r2 the MSB. The code is weighted 1, 2, and 4 from the LSB.
INTERNAL SPECIFICATIONS 4.3.3 Internal data memory 1-bit data designation In the MSM80C154S/MSM83C154S, 1-bit data manipulations (test, reset, set, complement, transfer) can be executed directly between internal data memory addresses 20 thru 2FH by bit manipulation instructions. The operation of a bit reset instruction is described below as an example. This instruction (CLR bit address) is a 2-byte 2-machine cycle instruction (see Figure 4-6).
MSM80C154S/83C154S/85C154HVS Table 4-4 Bit designation table Bit name b2 b1 b0 Bit 0 0 0 0 Bit 1 0 0 1 Bit 2 0 1 0 Bit 3 0 1 1 Bit 4 1 0 0 Bit 5 1 0 1 Bit 6 1 1 0 Bit 7 1 1 1 Table 4-5 Addressing combination table b7 b6 b5 b4 b3 RAM address 0 0 0 0 0 0 20H 32 1 0 0 0 0 1 21H 33 2 0 0 0 1 0 22H 34 3 0 0 0 1 1 23H 35 4 0 0 1 0 0 24H 36 5 0 0 1 0 1 25H 37 6 0 0 1 1 0 26H 38 7 0 0 1 1 1 27H 39 8 0 1 0 0
INTERNAL SPECIFICATIONS 4.4 Special Function Registers (TCON, SCON,.... ACC, B) 4.4.1 Outline As can be seen from the configuration shown in Table 4-6, the MSM80C154S/ MSM83C154S special function registers consist of 27 8-bit registers. Special function registers can be accessed (R/W) by either data addressing or bit addressing. All 27 registers can be specified by data addressing. 13 registers (P0, P1, P2, P3, TCON, T2CON, SCON, IE, IP, PSW, ACC, B, and IOCON) can be specified by bit addressing.
MSM80C154S/83C154S/85C154HVS Table 4-6 List of special function registers Bit address Register name b7 b6 b5 b4 b3 b2 b1 b0 IOCON FF FE FD FC FB FA F9 F8 0F8H(248) B F7 F6 F5 F4 F3 F2 F1 F0 0F0H(240) Data address ACC E7 E6 E5 E4 E3 E2 E1 E0 0E0H(224) PSW D7 D6 D5 D4 D3 D2 D1 D0 0D0H(208) TH2 0CDH(205) TL2 0CCH(204) RCAP2H 0CBH(203) RCAP2L 0CAH(202) T2CON CF CE CD CC CB CA C9 C8 0C8H(200) IP BF BE BD BC BB BA B9 B8 0B8H(184) P3 B
INTERNAL SPECIFICATIONS 4.4.2 Special function registers 4.4.2.1 Timer mode register (TMOD) Name Address MSB LSB 7 6 5 4 3 2 1 0 GATE C/T M1 M0 GATE C/T M1 M0 TMOD 89H Bit location Flag Function TMOD.0 M0 M1 M0 Timer/counter 0 mode setting TMOD.1 M1 0 0 8-bit timer/counter with 5-bit prescalar 0 1 16-bit timer/counter 1 0 8-bit timer/counter with 8-bit auto reloading 1 1 Timer/counter 0 separated into TL0 (8-bit) timer/counter and TH0 (8-bit) timer/counter.
MSM80C154S/83C154S/85C154HVS 4.4.2.2 Power control register (PCON) Name Address PCON 87H Bit location Flag PCON.0 IDL MSB LSB 7 6 5 4 3 2 1 0 SMOD HPD RPD — GF1 GF0 PD IDL Function IDLE mode set when this bit is set to "1". CPU operations are stopped when IDLE mode is set, but XTAL1·2, timer/counters 0, 1, and 2, the interrupt circuits, and serial port remain active. IDLE mode is cancelled when the CPU is reset or when an interrupt is generated. PCON.
INTERNAL SPECIFICATIONS 4.4.2.3 Timer control register (TCON) Name Address TCON 88H Bit location Flag TCON.0 IT0 TCON.1 IE0 MSB LSB 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Function External interrupt 0 signal used in level detect mode when this bit is "0", and in trigger detect mode when "1". Interrupt request flag for external interrupt 0. Bit is reset automatically when interrupt is serviced. Bit can be set and reset by software when IT0="1". TCON.
MSM80C154S/83C154S/85C154HVS 4.4.2.4 Serial port control register (SCON) Name Address SCON 98H Bit location Flag SCON.0 RI MSB LSB 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Function "End of serial port reception" interrupt request flag. This flag must be reset by software during interrupt service routine. This flag is set after the eighth bit of data has been received when in mode 0, or by the STOP bit when in any other mode.
INTERNAL SPECIFICATIONS 4.4.2.5 Interrupt enable register (IE) Name Address IE 0A8H Bit location Flag IE.0 EX0 MSB LSB 7 6 5 4 3 2 1 0 EA — ET2 ES ET1 EX1 ET0 EX0 Function Interrupt control bit for external interrupt 0. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.1 ET0 Interrupt control bit for timer interrupt 0. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.2 EX1 Interrupt control bit for external interrupt 1 .
MSM80C154S/83C154S/85C154HVS 4.4.2.6 Interrupt priority register (IP) Name Address IP 0B8H Bit location Flag IP.0 PX0 MSB LSB 7 6 5 4 3 2 1 0 PCT — PT2 PS PT1 PX1 PT0 PX0 Function Interrupt priority bit for external interrupt 0. Priority is assigned when bit is "1". IP.1 PT0 Interrupt priority bit for timer interrupt 0. Priority is assigned when bit is "1". IP.2 PX1 IP.3 PT1 IP.4 PS IP.5 PT2 IP.6 — IP.7 PCT Interrupt priority bit for external interrupt 1 .
INTERNAL SPECIFICATIONS 4.4.2.7 Program status word register (PSW) Name Address PSW 0D0H Bit location Flag PSW.0 P MSB LSB 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Function Accumulator (ACC) parity indicator. "1" when the "1" bit number in the accumulator is an odd number, and "0" when an even number. PSW.1 F1 User flag which may be set to "0" or "1" as desired by the user. PSW.
MSM80C154S/83C154S/85C154HVS 4.4.2.8 I/O control register (IOCON) Name Address IOCON 0F8H Bit location Flag IOCON.0 ALF MSB LSB 7 6 5 4 3 2 1 0 — T32 SERR IZC P3HZ P2HZ P1HZ ALF Function If CPU power down mode (PD, HPD) is activated with this bit set to "1", the outputs from ports 0, 1, 2, and 3 are switched to floating status. When this bit is "0", ports 0, 1, 2, and 3 are in output mode. IOCON.1 P1HZ Port 1 becomes a high impedance input port when this bit is "1". IOCON.
INTERNAL SPECIFICATIONS 4.4.2.9 Timer 2 control register (T2CON) Name Address TMOD 0C8H Bit location Flag T2CON.0 CP/RL2 MSB LSB 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Function Capture mode is set when TCLK+RCLK="0" and CP/RL2 16-bit auto reload mode is set when TCLK+RCLK="0" and CP/RL2="0". CP/RL2 is ignored when TCLK+RCLK="1". T2CON.1 C/T2 Timer/counter 2 count clock designation control bit.
MSM80C154S/83C154S/85C154HVS 4.5 Timer/Counters 0, 1 and 2 4.5.1 Outline Timer/counters 0, 1 and 2 are all equipped with 16-bit binary up-counting and Read/Write functions, and can be operated independently. All control of timer/counters 0 and 1 is handled by the timer control register (TCON 88H) and the timer mode register (TMOD 89H). And both timer/counters can be set independently to modes 0 thru 3 for a diversity of applications.
77 INT0 PIN (PORT 3.2) T0 PIN (PORT 3.4) INT1 PIN (PORT 3.3) T1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 4.5.2.3 Timer/counter 0 and 1 count clock designation Designation of count clock inputs to timer/counters 0 and 1 is controlled by bit 2 and 6, C/T, in the timer mode register (TMOD 89H). Timer/counter 0 is controlled by bit 2, C/T, and timer/counter 1 is controlled by bit 6, C/T. The internal clock is passed to the timer/counter when the C/T bit is “0”. This internal clock is the result of dividing XTAL1·2 by 12. The S3 timing signal (see Figure 2-9) becomes the clock.
INTERNAL SPECIFICATIONS 4.5.2.3.1 External clock detector circuit for timer/counters 0 and 1 The detector circuit shown in Figure 4-8 is inserted between the timer/counters and the external clock pin. This detector circuit operates in the following way. When the external clock applied to the T0 and T1 pins is changed from “1” to “0” level, that clock is fetched by F/Fl, and is then passed to F/F2 when the S5 timing signal appears.
MSM80C154S/83C154S/85C154HVS M1 S6 XTAL1 1 0 ALE 1 0 T0 or T1 COUNT IN 1 0 F/F1Q 1 0 F/F2Q 1 0 TIMER COUNT 1 0 S1 S2 S3 M1 or M2 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 Figure 4-9 Detector circuit operational time chart 4.5.2.
INTERNAL SPECIFICATIONS ÷12 XTAL 1 T0 or T1 S3 TIMER 0 or TIMER 1 CLOCK DETECTOR C/ T INT0 or INT1 D S5 Q L ✽ GATE TR0 or TR1 Figure 4-10 INT0 and INT1 timer/counter start/stop control circuit Table 4-10 GATE·INT·TR timer/counter control tables TIMER 0 TIMER 1 GATE 0 0 1 1 1 GATE 0 0 1 1 1 TR0 0 1 0 1 1 TR1 0 1 0 1 1 INT0 × × 0 0 1 INT1 × × 0 0 1 • RUN • • • • RUN STOP • • STOP 81 • • •
MSM80C154S/83C154S/85C154HVS 4.5.2.5 Timer/counters 0/1 timer modes 4.5.2.5.1 Outline The timer/counter 0 and 1 timer modes are set by combinations of M0 and M1 bit data in the timer mode register (TMOD 89H) shown in Table 4-11. The timer modes which can be set are 0, 1, 2, and 3. Timer/counter 0 modes are specified by M0 and M1 of bits 0 and 1, and timer/counter 1 modes are specified by M0 and M1 of bits 4 and 5.
INTERNAL SPECIFICATIONS XTAL 1 T0 PIN (PORT 3.4) ÷12 S3 DETECTOR Q0------Q4 TL0 (5BITS) DETECTOR TF0 Q0------Q7 TH0 C (8BITS) C/ T TR0 GATE INT0 PIN (PORT 3.2) S5 DATA LATCH Q Figure 4-11 Timer/counter 0 mode 0 XTAL 1 T1 PIN (PORT 3.5) ÷12 S3 DETECTOR Q0------Q4 TL1 (5BITS) DETECTOR Q0------Q7 TH1 C (8BITS) C/ T TR1 S I/O CLOCK GATE INT1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 4.5.2.5.3 Mode 1 M1 M0 0 1 In mode 1, timer/counters 0 and 1 both become 16-bit timer/counters by the circuit connection shown in Figures 4-13 and 4-14. TL0 and TL1 in timer/counters 0 and 1 serve as the counter for the eight lower bits, and TH0 and TH1 serve as the counter for the eight upper bits. TL0 is set by the timer/counter 0 carry signal, and TF1 is set by the timer/counter 1 carry signal.
INTERNAL SPECIFICATIONS XTAL 1 T0 PIN (PORT 3.4) ÷12 S3 DETECTOR Q0------Q7 TL0 (8BITS) DETECTOR TF0 Q0------Q7 TH0 C (8BITS) C/ T TR0 GATE INT0 PIN (PORT 3.2) S5 DATA LATCH Q Figure 4-13 Timer/counter 0 model XTAL 1 T1 PIN (PORT 3.5) ÷12 S3 DETECTOR Q0------Q7 TL1 (8BITS) DETECTOR Q0------Q7 TH1 C (8BITS) C/ T TR1 S I/O CLOCK GATE INT1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 4.5.2.5.4 Mode 2 M1 M0 1 0 In mode 2, timer/counters 0 and 1 both become 8-bit timer/counters with 8-bit auto reloader registers by the circuit connection shown in Figures 4-15 and 4-16. TH0 and TH1 in timer/ counters 0 and 1 serve as the 8-bit auto reloader section, and TL0 and TL1 serve as the timer/ counter section.
INTERNAL SPECIFICATIONS XTAL 1 T0 PIN (PORT 3.4) ÷12 S3 DETECTOR TF0 Q0------Q7 TL0 C (8BITS) DETECTOR C/ T TR0 Q0------Q7 TH0 (8BITS) GATE INT0 PIN (PORT 3.2) S5 DATA LATCH RELOAD DATA Q Figure 4-15 Timer/counter 0 mode 2 S I/O CLOCK XTAL 1 T1 PIN (PORT 3.5) ÷12 S3 DETECTOR Q0------Q7 TL1 C (8BITS) DETECTOR C/ T TR1 Q0------Q7 TH1 (8BITS) GATE INT1 PIN (PORT 3.
MSM80C154S/83C154S/85C154HVS 4.5.2.5.5 Mode 3 M1 M0 1 1 In mode 3, timer/counter 0 TL0 and TH0 become independent 8-bit timer/counters by the circuit connection shown in Figure 4-17. Timer/counter 1 does not operate when mode 3 is set. The TL0 8-bit timer/counter is controlled in the same way as the regular timer/counter 0, TF0 being set if a carry signal is generated by TL0. The TH0 8-bit timer/counter is controlled only by TR1, and the control only covers count starting and stopping.
INTERNAL SPECIFICATIONS 4.5.2.5.6 32-bit timer mode When “1” is set in bit 6 (T32) of the I/O control register (IOCON 0F8H), timer/counters 0 and 1 are connected serially as indicated in Figure 4-18 to become a 32-bit timer/counter. This 32-bit timer/counter is started by the following procedure. First, “0” is set in TR0, TR1, TF0, and TF1 of the timer control register (TCON 88H) to stop the timer/counter and reset the timer flag.
MSM80C154S/83C154S/85C154HVS 4.5.2.5.7 Caution about use of timer counters 0 and 1 Since the internal clock stops operation during soft power down mode (PD), the auto-reload operation is not executed if timer/counters 0 and 1 are set to mode 2 or mode 3. If the power down mode is to be cancelled by the timer, timer/counters 0 and 1 must be set to mode 0 or mode 1.
INTERNAL SPECIFICATIONS 4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software power down mode When setting sofware power down mode, if the value of a timer counter by which a timer interrupt is set is immediately before overflow, the software power down mode can not be set. (Example) Timer 0 is in mode 1 of external clock. Content of timer 0 is "FF". Interrupt by timer 0 is enabled. TO pin is "1". If the above conditions all are established, the sofware power down mode cannot be set.
MSM80C154S/83C154S/85C154HVS 4.5.3 Timer/counter 2 4.5.3.1 Outline Timer/counter 2 is equipped with 16-bit binary counting and Read/Write functions. This timer/ counter is controlled entirely by timer 2 control register (T2CON 0C8H). The operating modes are 16-bit auto reload mode, capture mode, and baud rate generator mode. Modes are specified by T2CON RCLK, TCLK, and CP/RL2 bits combinations. The internal or external clock applied to the timer/counter 2 is specified by the C/T2 bit.
INTERNAL SPECIFICATIONS EXF2 : TF2 : Timer/counter 2 external flag bit which is set when the T2EX pin level (bit 1 of port 1) is changed from “1” to “0” at EXEN2=1. This flag serves as the timer interrupt 2 request signal. When an interrupt is generated, this flag must be reset to “0” by software. Timer/counter 2 internal flag bit which is set when a carry signal is generated by timer/counter 2 in 16-bit auto reload mode or capture mode. This flag serves as the timer interrupt 2 request signal.
MSM80C154S/83C154S/85C154HVS XTAL 1 ÷12 S3 RCLK=0 TCLK=0 CP/ RL2=0 Q0------Q7 TL2 C 8 BIT C/ T2 Q0------Q7 TH2 C 8 BIT TR2 T2 DETECTOR RCAP2L [PORT 1.0] T2EX RCAP2H DETECTOR TF2 DETECTOR EXF2 DETECTOR [PORT 1.1] TIMER 2 INTERRUPT EXEN2 Figure 4-20 Timer/counter 2 16-bit auto reload mode circuit 4.5.3.3.2 16-bit capture mode The 16-bit capture mode is set by making the connections shown in Figure 4-21 with the following timer 2 control register (T2CON) bit conditions, viz.
INTERNAL SPECIFICATIONS XTAL 1 ÷12 S3 RCLK=0 TCLK=0 CP/ RL2=1 Q0------Q7 TL2 C 8 BIT C/ T2 Q0------Q7 TH2 C 8 BIT TR2 T2 DETECTOR RCAP2L [PORT 1.0] RCAP2H DETECTOR TF2 DETECTOR EXF2 T2EX DETECTOR [PORT 1.1] TIMER 2 INTERRUPT EXEN2 Figure 4-21 Timer/counter 2 16-bit capture mode circuit 4.5.3.3.3 16-bit baud rate generator mode The 16-bit baud rate generator mode is set by making the connections shown in Figure 4-22 with the following timer 2 control register (T2CON) bit conditions, viz.
*RCLK+TCLK=1 CP/ RL2=× 96 Figure 4-22 Timer/counter 2 baud rate generator mode circuit TIMER 1 OVERFLOW ÷16 RX CLOCK [MODE1, 3] ÷16 TX CLOCK [MODE1, 3] ÷2 XTAL 1 S3 ÷2 RCLK Q0------Q7 TL2 C 8 BIT C/ T2 Q0------Q7 TH2 C 8 BIT TR2 T2 [PORT 1.0] DETECTOR RCAP2L RCAP2H TCLK T2EX [PORT 1.
INTERNAL SPECIFICATIONS 4.5.3.4 Timer/counter 2 detector circuit 4.5.3.4.1 T2 (timer/counter 2 external clock detector) The T2 detector circuit block diagram is shown in Figure 4-23. Operation of this circuit is outlined below. When the level of the signal applied to T2 (bit 0 of port 1) is changed from “1” to “0”, output of F/Fl becomes “1”. This output signal is then passed to F/F2 at S5 timing and F/F2 output also becomes “1”.
MSM80C154S/83C154S/85C154HVS 4.5.3.5 Timer/counter carry signal detector circuit The detector circuit shown in Figure 4-25 is inserted between the MSM80C154S/ MSM83C154S timer/counter carry output and the timer flag.
INTERNAL SPECIFICATIONS 4.6 Serial Port 4.6.1 Outline MSM80C154S/MSM83C154S is equipped with a serial port which can be used in I/O extension and UART (Universal Asynchronous Receiver/Transmitter) applications. I/O extension mode • Input and output of 8-bit serial data synchronized with the MSM80C154S/MSM83C154S output clock. UART mode • Independent transmitter and receiver circuits for full duplex communication.
MULTIPLEXER SBUF (T) TIMER/COUNTER1 OVERFLOW TIMER/COUNTER2 OVERFLOW 1/2OSC. TXD (P3.1) SHIFT CLOCK TX CONTROL 100 Figure 4-27 Serial port (PCON.7) (T2CON.4) SCON SMOD TCLK (T2CON.5) (IOCON.5) RCLK SERR RX CONTROL INPUT SHIFT REGISTER Note: MULTIPLEXER : Internal bus connection : Serial data flow and shift clock : Control coupling RXD (P3.
INTERNAL SPECIFICATIONS 4.6.2 Special function registers for serial port 4.6.2.1 SCON (Serial Port Control Register) SCON is an 8-bit special function register consisting of control bits for specifying serial port operation modes and enabling/disabling data reception, storage bits for the ninth data bit transmitted and received during 11-bit frame UART mode, and the serial port status flag. In addition to specifying SCON by data address 98H, each bit can be specified by bit addresses.
MSM80C154S/83C154S/85C154HVS Table 4-15 SCON Bit Symbol 0 RI Function "End of reception" flag. This is the interrupt request flag set by hardware when reception of one frame has been completed. The interrupt is generated by ORing with the T1 flag. Since the flag cannot be cleared by hardware, it must be cleared by software. 1 TI "End of transmission" flag. This is the interrupt request flag set by hardware when transmission of one frame has been completed.
INTERNAL SPECIFICATIONS Table 4-16 Serial port operation modes SM0 SM1 Mode 0 0 0 I/O extension Function 1/12 FOSC Baud rate 0 1 1 10-bit frame UART Vareable 1 0 2 11-bit frame UART 1/32 FOSC or 1/64 FOSC 1 1 3 11-bit frame UART Vareable Note: FOSC denotes frequency of fundamental oscillator (XTAL1·2). 4.6.2.2 SBUF (serial port buffer register) SBUF is an 8-bit special function register used to store transmitting and receiving data.
MSM80C154S/83C154S/85C154HVS 4.6.2.5 SMOD SMOD controls the division of the baud rate clock source when the serial port is in UART mode (mode 1, 2, or 3). If SMOD is cleared when in mode 1 or 3, the timer/counter 1 overflow frequency divided by 2 becomes the baud rate clock source. And if SMOD is set, the timer/counter 1 overflow becomes the baud rate clock source.
INTERNAL SPECIFICATIONS 4.6.2.6 SERR SERR is the status flag set when a framing error or overrun error is generated during UART mode (mode 1, 2, or 3). Framing error: The SERR flag is set when no stop bit is detected in UART mode. Framing error is detected irrespective of the data reception conditions set by SM2. Overrun error: The SERR flag is also set when the next data is ready to be transferred from the input shift register to the SBUF which is already full in UART mode.
MSM80C154S/83C154S/85C154HVS 4.6.3 Operating modes 4.6.3.1 Mode 0 4.6.3.1.1 Outline Mode 0 is the I/O extension mode where input and output of 8-bit data via RXD (P3.0) is synchronized with the output clock from TXD (P3.1). The baud rate in mode 0 is fixed to 1/12th of the fundamental oscillator (XTAL1·2) frequency to enable the serial port to operate synchronized with the basic MSM80C154S/MSM83C154S timing.
INTERNAL BUS SHIFT CLOCK WRITE TO SBUF START SBUF (T) TXD ENABLE 107 SERIAL PORT INTERRUPT REN START RI RXD INPUT SHIFT REG.
108 Figure 4-29 Serial port (mode 0) timing chart RI TERMINATE TRANSMISSION LOAD SBUF SHIFT-IN CLOCK TXD READ RXD REN·RI D1 D2 D3 D4 D5 D6 D7 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 WRITE TO SCON ALE TI TERMINATE TRANSMISSION TXD RXD D0 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
TXD (SHIFT CLOCK) READ RXD TXD (SHIFT CLOCK) INPUT: RXD (DATA OUTPUT) OUTPUT: ALE XTAL1 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 INTERNAL SPECIFICATIONS Figure 4-30 Serial port (mode 0) timing and corresponding basic MSM80C154S/ MSM83C154S timing 109
MSM80C154S/83C154S/85C154HVS 4.6.3.2 Mode 1 4.6.3.2.1 Outline Mode 1 is the 10-bit frame UART mode (with one start bit, eight data bits, and one stop bit) where the baud rate may be set to any value depending on the timer/counter 1 or timer/ counter 2 setting. A block diagram of the serial port in mode 1 is shown in Figure 4-31, and the operational timing chart is given in Figure 4-32. 4.6.3.2.
INTERNAL SPECIFICATIONS B = fOSC × 1 1 1 × × 2 65536-DRCAP2 16 where B is the baud rate, fOSC the fundamental frequency (XTAL1·2), and DRCAP2 the contents of RCAP2L and RCAP2H (expressed in decimal). 4.6.3.2.3 Mode 1 transmit operation The transmit basic clock (TXCLOCK in Figure 4-31) is obtained from the overflow of a hexadecimal free-run counter where the timer/counter 1 or timer/counter 2 overflow is used as the clock. Transmission is commenced when transmit data is written in SBUF.
MSM80C154S/83C154S/85C154HVS 4.6.3.2.5 Mode 1 UART error detection If the following two conditions are satisfied when the hexadecimal counter is in state 10 during reception of the stop bit, it is assumed that new data is received before processing of the previously received data has been completed. Hence, an overrun error is generated, and the new data is lost. The SERR flag is set at the first M1·S3 after the hexadecimal counter has reached state 10. Note that the previous SBUF (R) data is preserved.
INTERNAL BUS WRITE TO SBUF START TCLK TCLK=1 SBUF TI START RI TCLK=0 SERIAL PORT INTERRUPT SERR RXD SAMPLE LOGIC INPUT SHIFT REG.
114 RI or SERR SET TERMINATE RECEPTION LOAD SBUF SHIFT-IN CLOCK RXD SAMPLE CLOCK RX COUNTER RUN RXD TI TERMINATE TRANSMISSION TXD WRITE TO SBUF TX CLOCK START BIT START BIT D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 STOP BIT M1·S3 STOP BIT M1·S3 MSM80C154S/83C154S/85C154HVS Figure 4-32 Serial port (mode 1) timing chart
INTERNAL SPECIFICATIONS 4.6.3.3 Mode 2 4.6.3.3.1 Outline Mode 2 is an 11-bit frame UART mode (with one start bit, eight data bits, one multipurpose data bit, and one stop bit) where the baud rate is 1/64th or 1/32nd of the fundamental oscillator (XTAL1·2) frequency. A block diagram of the serial port in mode 2 is shown in Figure 4-33, and the operational timing chart is given in Figure 4-34. 4.6.3.3.
MSM80C154S/83C154S/85C154HVS When this “1” to “0” RXD change is detected, the hexadecimal counter which had been stopped in reset status commences to count up. When the hexadecimal counter is in state 7, 8, and 9, the start bit is sampled, and is accepted as valid if at least two of the three sampled values are “0”, thereby enabling data reception to continue.
INTERNAL BUS WRITE TO SBUF START SMOD 117 1/2 SBUF BAUD RATE CLOCK 1/16 COUTER TI START RI TXD (T) SMOD=0 SERIAL PORT INTERRUPT SERR RXD SAMPLE LOGIC INPUT SHIFT REG.
118 RI or SERR SET TERMINATE RECEPTION LOAD SBUF SHIFT-IN CLOCK RXD SAMPLE CLOCK RX COUNTER RUN RXD TI START BIT TERMINATE TRANSMISSION TXD WRITE TO SBUF TX CLOCK START BIT D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 RBB STOP BIT TBB M1·S3 M1·S3 STOP BIT MSM80C154S/83C154S/85C154HVS Figure 4-34 Serial port (mode 2) timing chart
INTERNAL SPECIFICATIONS 4.6.3.4 Mode 3 4.6.3.4.1 Outline Mode 3 is another 11-bit frame UART mode (with one start bit, eight data bits, one multipurpose data bit, and one stop bit). Whereas the baud rate is 1/64th or 1/32nd of the fundamental oscillator frequency in mode 2, the mode 3 baud rate can be freely selected according to the timer/counter 1 or timer/counter 2 setting. Apart from the ability to vary the baud rate, mode 3 is identical to mode 2.
MSM80C154S/83C154S/85C154HVS B = fOSC × 1 1 1 × × 2 65536-DRCAP2 16 where B is the baud rate, fOSC the fundamental oscillator (XTAL1·2) frequency, and DRCAP2 the contents of RCAP2L and RCAP2H (expressed in decimal). 4.6.3.4.3 Mode 3 transmit operation The transmit basic clock (TXCLOCK in Figure 4-36) is obtained from a hexadecimal free-run counter overflow where timer/counter 1 or timer/counter 2 overflow is used as the clock. Transmission is commenced when transmit data is written in SBUF.
INTERNAL SPECIFICATIONS If the above conditions are not satisfied when the hexadecimal counter is in state 10 during the multi-purpose data bit interval, the received data is disregarded, the SBUF, RB8, and RI flags remain unchanged, and the receive circuit is initialized when the hexadecimal counter is in state 10 during the stop bit interval.
WRITE TO SBUF START TCLK TCLK=1 SBUF Figure 4-35 Serial port (mode 3) 122 BAUD RATE CLOCK 1/16 COUTER TI START RI TXD (T) TCLK=0 SERIAL PORT INTERRUPT SERR RXD SAMPLE LOGIC INPUT SHIFT REG.
123 RI or SERR SET TERMINATE RECEPTION LOAD SBUF SHIFT-IN CLOCK RXD SAMPLE CLOCK RX COUNTER RUN RXD TI START BIT TERMINATE TRANSMISSION TXD WRITE TO SBUF TX CLOCK START BIT D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 RBB STOP BIT TBB M1·S3 M1·S3 STOP BIT INTERNAL SPECIFICATIONS Figure 4-36 Serial port (mode 3) timing chart
MSM80C154S/83C154S/85C154HVS 4.6.4 Serial port application examples 4.6.4.1 I/O extension I/O extension can be achieved by using the serial port in mode 0. An input extension example is shown in Figure 4-37 and the corresponding timing chart is shown in Figure 4-38. Following output of the latch pulse from PX.X, REN=“1” and R1=“0” are set for shift in of 74LS1 65 data. MSM80C154S MSM83C154S RXD VCC SHIFT/ LOAD QH SERIAL IN CLOCK 74LS165 INHIBIT CK H G F E D C B A PX.
INTERNAL SPECIFICATIONS An output extension example is shown in Figure 4-39 and the corresponding timing chart is shown in Figure 4-40. After output data has been written into SBUF and the output sequence completed, the latch pulse output from PX.X is obtained and the 74LS164 data is shifted to 74LS373. OUTPUT MSM80C154S MSM83C154S VCC 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 74LS373 OC G 8D 7D 6D 5D 4D 3D 2D 1D PX.X QHQG QF QE QDQC QB QA B A RXD 74LS164 CLK TXD CK Figure 4-39 Output extension example RXD TXD PX.
MSM80C154S/83C154S/85C154HVS OUTPUT VCC 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 74LS373 OC G 8D 7D 6D 5D 4D 3D 2D 1D PX.X MSM80C154S MSM83C154S QHQG QF QE QDQC QB QA B OUTPUT CONTROL A 74LS164 CLK CK 74LS126 RXD VCC SHIFT/ LOAD QH SERIAL IN CLOCK 74LS165 INHIBIT CK H G F E D C B A PX.
RXD INPUT CONTROL OUTPUT CONTROL TXD INPUT 74LS165 OUTPUT OUTPUT MSM80C154S/MSM83C154S OUTPUT INTERNAL SPECIFICATIONS In all examples, additional multiple bit I/O extension is made possible by multiple cascade connections of 74LS164 or 74LS165.
MSM80C154S/83C154S/85C154HVS 4.6.4.2 Multi-processor systems Multi-processor systems can be formed with MSM80C154S/MSM83C154S by using the serial port in mode 2 or mode 3 for inter-processor communications. If reception data bit 9 (multi-purpose data bit) is “1” when SM2 is set in mode 2 or 3, reception data is received and an interrupt is generated. If the data bit is “0”, however, the reception data is disregarded and no interrupt is generated.
4.7 Interrupt 4.7.1 Outline MSM80C154S/MSM83C154S is equipped with six interrupts. 1. INT0 External interrupt 0 2. TM0 Timer interrupt 0 3. INT1 External interrupt 1 4. TM1 Timer interrupt 1 5. SI/O Serial port interrupt 6. TM2 Timer interrupt 2 These six interrupts are controlled by interrupt enable register (IE) and interrupt priority register (IP). When the relevant interrupt conditions are met, the respective interrupt address is called and the interrupt routine is commenced.
INTERRUPT ENABLE REGISTER INTERRUPT PRIORITY REGISTER SOURCE ENABLE TCON.1 IE0 EXTERNAL INTERRUPT 0 TCON.3 IE1 EXTERNAL INTERRUPT 1 TCON.7 TF1 TIMER INTERRUPT 1 EX0 IP.1 PX1 EX0 IP.2 PT1 EX0 IP.3 PS EX0 IP.4 PT2 IE.0 IE.0 IE.0 IE.0 T2CON.7 TF2 T2CON.6 EXF2 TIMER INTERRUPT 2 EX0 IP.0 PT0 IE.0 SCON.0 RI SCON.0 TI SERIAL PORT INTERRUPT PX0 IE.0 PI NI INTERRUPT ADDRESS DATA PI NI PI NI PI NI PI NI PI NI IP.5 VCC VCC EA PCT IE.7 IP.
INTERNAL SPECIFICATIONS 4.7.2 Interrupt enable register (IE) The function of the interrupt enable register (IE, 0A8H) is to enable or disable interrupt processes when an interrupt is requested. To execute the intended interrupt routine, the interrupt is first enabled by setting “1” in the corresponding interrupt bit in the interrupt enable register, and the routine then is executed when the interrupt is requested.
MSM80C154S/83C154S/85C154HVS 4.7.3 Interrupt priority register (IP) The function of the interrupt priority register (IP, 0B8H) is to allocate rights to commence interrupt routines on a priority basis when an interrupt is requested. Interrupt priority can be programmed by setting the bit corresponding to the interrupt request in the interrupt priority register (IP) to “1”. If the interrupt conditions have been satisfied for an interrupt where “1” data has been set, processing of that interrupt is commenced.
INTERNAL SPECIFICATIONS 4.7.3.1 Priority interrupt routine flow The flow of interrupt processing when a priority interrupt is generated and processed after a routine has been commenced by a non-priority interrupt generated during execution of a main routine program is outlined in Figure 4-45 below. This diagram shows the flow chart up to the point of return to the main routine.
MSM80C154S/83C154S/85C154HVS 4.7.3.2 Interrupt routine flow when priority circuit is stopped When bit 7 (PCT) of the priority register (IP 0B8H) is set to “1”, all interrupt control is transferred to the interrupt enable register (IE 0A8H). When this mode is set, the interrupt disable instruction (CLR EA) must always be placed at the beginning of the interrupt routine to prevent any other interrupt from being generated.
INTERNAL SPECIFICATIONS 4.7.3.3 Interrupt priority when priority register (IP) contents are all “0” The interrupt priority when the priority register (IP, 0B8H) contents are all “0” indicates the priority in which a certain interrupt is processed in preference to other interrupts when interrupt requests are generated simultaneously.
MSM80C154S/83C154S/85C154HVS 4.7.4 Detection of external interrupt signals INT0 and INT1 4.7.4.1 Outline of INT signal detection Detect modes of the external interrupt signals 0 and 1 can be set to level-detect or triggerdetect mode by the IT0 and IT1 data values in the timer control register (TCON 88H) as indicated in Table 4-22. Table 4-22 TCON[88H] register INT1 Timer INT0 Bit 7 6 5 4 3 2 1 0 Flag TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Set • • 4.7.4.
INTERNAL SPECIFICATIONS 4.7.4.3 External interrupt signal 0 and 1 trigger detection When bit 0 (IT0) in the timer Control register (TCON 88H) is “1”, external interrupt 0 is edgeactivated. And when bit 2 (IT1) is “1”, external interrupt 1 is also edge-activated. With the external interrupt signals in trigger-detect mode, external interrupts 0 and 1 are triggerdetected by the equivalent circuit shown in Figure 4-48.
MSM80C154S/83C154S/85C154HVS 4.7.5 MSM80C154S/MSM83C154S interrupt response time charts 4.7.5.1 Interrupt response time chart when interrupt conditions are satisfied during execution of ordinary instructions in main routine If interrupt conditions are satisfied during execution of an ordinary instruction (which does not manipulate IE or IP) in the main routine, the MSM80C154S/MSM83C154S calls the interrupt address in the next cycle following completion of the ordinary instruction.
139 Timer flag 1 Instruction execution ALE XTAL1 0 1- 0- 1 0 1- S6 S2 S3 S4 S5 S6 Execution of one instruction S1 M1~M4 M1 or M2 S2 S3 S4 S5 S6 Execution of one instruction S1 M1~M4 M1 or M2 S1 S2 S3 S5 S6 S1 S2 S4 M2 S3 Timer 1 interrput address call S4 M1 S5 S6 INTERNAL SPECIFICATIONS Figure 4-49 lnterrupt response time chart when interrupt conditions are satisfied during execution of ordinary instruction in main routine
MSM80C154S/83C154S/85C154HVS 4.7.5.
141 Timer flag 1 Instruction execution ALE XTAL1 0 1- 0- 1 0 1- S6 S1 S3 S4 S5 Execution of IE or IP manipulation instruction S2 M1 or M2 S6 S2 S3 S4 S5 S6 Execution of one instruction S1 M1~M4 M1 or M2 S1 S2 S3 S5 S6 S1 S2 S4 M2 S3 Timer 1 interrput address call S4 M1 S5 S6 INTERNAL SPECIFICATIONS Figure 4-50 Interrupt response time chart when interrupt conditions are satisfied during execution of IE or IP register manipulating instruction in main routine
MSM80C154S/83C154S/85C154HVS 4.7.5.
143 Timer flag 1 Instruction execution ALE XTAL1 0 1 0- 1 0 1- S6 S1 S3 S4 S5 RETI execution S2 M2 S6 S1 S3 S4 S5 Execution of one ordinary main routine instruction S2 M1~M4 M1 or M2 S6 S1 S2 S3 S5 S6 S1 S2 S4 M2 S3 Timer 1 interrput address call S4 M1 S5 S6 INTERNAL SPECIFICATIONS Figure 4-51 Interrupt response time chart when ordinary instruction is executed after returning to main routine during continuous interrupt processing
MSM80C154S/83C154S/85C154HVS 4.7.5.
145 Timer flag 1 Instruction execution ALE XTAL1 0 1 0- 1 0 1- S6 S1 S3 S4 S5 RETI execution S2 M2 S6 S1 S3 S4 S5 Execution of IE or IP manipulation instruction S2 M1 or M2 S6 S2 S3 S4 S5 S6 Execution of one instruction S1 M1~M4 M1 or M2 S2 S3 S4 S5 S6 Timer 1 interrput address call S1 M1 INTERNAL SPECIFICATIONS Figure 4-52 Interrupt response time chart when IE or IP manipulating instruction is executed after returning to main routine during continuous interrupt pro
MSM80C154S/83C154S/85C154HVS 4.8 CPU “Power Down” 4.8.1 Outline Since the internal MSM80C154S/MSM83C154S circuits have been designed as completely static circuits, all internal information (register data) is preserved if XTAL1·2 oscillation is stopped. This feature is utilized to incorporate a fuller range of power down modes. In idle mode (IDLE) where “1” is set in bit 0 (IDL) of the power control register (PCON), XTAL1·2 operation is continued but CPU operations are stopped.
INTERNAL SPECIFICATIONS XTAL 2 TIMER, S-I/O & INTERRUPT CPU CONTROL CLOCK XTAL 1 CONTROL PCON, 87H Bit Set SMOD HPD RPD — GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 * • Figure 4-53 ldle mode equivalent circuit 147
MSM80C154S/83C154S/85C154HVS Table 4-23 CPU pin details in idle mode Name P1.0/T2 Internal ROM Port data output External ROM Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.3 Port data output Port data output P1.4 Port data output Port data output P1.5 Port data output Port data output P1.6 Port data output Port data output P1.7 Port data output Port data output RESET “0” level input “0” level input P3.
IDLE SET CYCLE S4 PORT DATA S3 PORT DATA S2 1 0 S1 PORT 3 S6 PORT DATA 1 0 PORT 0 S5 1 0 1 0 *PCON-bit 0 S4 PORT 2 1 0 W-PCON S3 PORT DATA 1 0 PSEN S2 1 0 1 0 ALE S1 M1 PORT 1 1 0 XTAL1 S6 M1 or M2 S5 S6 S1 S3 S4 IDLE MODE S2 M1 S5 S6 S1 S2 S3 M1 S4 S5 S6 INTERNAL SPECIFICATIONS Figure 4-54 Idle mode setting time chart (internal ROM mode) 149
S2 S4 FLOATING S3 150 IDLE SET CYCLE PORT DATA 1 0 PCH PCL S1 PORT 3 PCH PCL S6 PCH 1 PCL 0 PORT 0 S5 1 0 1 0 *PCON-bit 0 S4 PORT 2 1 0 W-PCON S3 PORT DATA 1 0 PSEN S2 1 0 1 0 ALE S1 M1 PORT 1 1 0 XTAL1 S6 M1 or M2 S5 S6 S1 S3 S4 IDLE MODE S2 M1 S5 S6 S1 S2 S3 M1 S4 S5 S6 MSM80C154S/83C154S/85C154HVS Figure 4-55 Idle mode setting time chart (external ROM mode)
INTERNAL SPECIFICATIONS 4.8.3 Soft power down mode (PD) setting Soft power down mode (PD) is set when “1” is set in bit 1 (PD) of the power control register (PCON 87H). The circuit connection involved in this setting is shown in Figure 4-56. Soft power down mode cancellation conditions can be set through manipulation of bit 5 (RPD) of the power control register.
152 Figure 4-56 Soft power down mode equivalent circuit CPU CLOCK XTAL 1 CONTROL I/O FLOATING PCON 87H Bit SMOD HPD RPD — GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 Set * • IOCON 0F8H Bit Set — T32 SERR IZC P3HZ P2HZ P1HZ ALF 7 6 5 4 3 2 1 0 • MSM80C154S/83C154S/85C154HVS XTAL 2
INTERNAL SPECIFICATIONS PD PCON5(RPD) S3 INT0 or INT1 D Q S RESET L S5 IE0 or 1 PDRESET Q R S6 M END Figure 4-57 Power down cancellation circuit at INTERRUPT level input INT0 or INT1 D L S5 Q D L Q S3 PCON5(RPD) PD S4 IE0 or 1 S S3 BUS S2 W TCON PDRESET Q D LR RESET Figure 4-58 Power down cancellation circuit at INTERRUPT edge input 153
MSM80C154S/83C154S/85C154HVS F/F1 VCC D Q D F/F1 T0 or T1 TIMER0, 1 C F/F2 Q F/F2 L R S5 SQ RESET S3 RESET PD R TF0 or 1 PCON5(RPD) Figure 4-59 TIMER0, 1 power down cancellation circuit 154 PDRESET
INTERNAL SPECIFICATIONS Table 4-24 CPU pin details (ALF=0) in soft power down mode (PD) Name P1.0/T2 Internal ROM Port data output External ROM Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.3 Port data output Port data output P1.4 Port data output Port data output P1.5 Port data output Port data output P1.6 Port data output Port data output P1.7 Port data output Port data output RESET “0” level input “0” level input P3.
1 0 1 0 1 0 1 0 1 0 ALE PSEN IOCON-bit 0 W-PCON *PCON-bit 1 156 S3 S4 S5 PORT DATA 1 0 PORT 3 PORT DATA PORT DATA PORT DATA PORT DATA *ALF=“0” SOFT POWER DOWN MODE PORT DATA PORT DATA 1 0 S1 PORT 2 S6 PORT DATA PD SET CYCLE S2 1 0 S1 M1 PORT 1 PORT 0 1 0 XTAL1 S6 M1 or M2 MSM80C154S/83C154S/85C154HVS Figure 4-60 Soft power down mode setting time chart (internal ROM mode)
157 PD SET CYCLE PORT DATA PORT DATA PORT DATA FLOATING *ALF=“0” SOFT POWER DOWN MODE PORT DATA 1 0 PCH PORT 3 PCH PORT DATA PCH PCL 1 0 PCL S6 PORT 2 1 0 *PCON-bit 1 S5 PORT DATA 1 0 W-PCON S4 1 0 1 0 IOCON-bit 0 S3 PORT 1 1 0 PSEN S2 1 PCL 0 1 0 ALE S1 M1 PORT 0 1 0 XTAL1 S6 M1 or M2 INTERNAL SPECIFICATIONS Figure 4-61 Soft power down mode setting time chart (external ROM mode)
MSM80C154S/83C154S/85C154HVS Table 4-25 CPU pin details (ALF=1) in soft power down mode (PD) Name Internal ROM External ROM P1.0/T2 Floating Floating P1.1/T2EX Floating Floating P1.2 Floating Floating P1.3 Floating Floating P1.4 Floating Floating P1.5 Floating Floating P1.6 Floating Floating P1.7 Floating Floating RESET “0” level input “0” level input P3.0/RXD Floating Floating P3.1/TXD Floating Floating P3.2/ INT0 External data input External data input P3.
159 PORT DATA PORT DATA 1 0 1 0 PORT 2 PORT 3 S4 S5 PD SET CYCLE PORT DATA 1 0 PCON-bit 1 1 0 1 0 W-PCON PORT 1 1 0 IOCON-bit 0 S3 PORT DATA 1 0 PSEN S2 1 0 1 0 ALE S1 *PORT 0 1 0 XTAL1 S6 M1 or M2 S6 S1 FLOATING FLOATING FLOATING FLOATING *ALF=“1” SOFT POWER DOWN MODE M1 INTERNAL SPECIFICATIONS Figure 4-62 Soft power down mode setting and I/O floating time chart (internal ROM mode)
1 0 1 0 PORT 3 1 0 *PCON-bit 1 PORT 2 1 0 W-PCON 1 0 1 0 IOCON-bit 0 PORT 1 1 0 PSEN 1 PCL 0 1 0 ALE PORT 0 1 0 XTAL1 S6 PCH S1 S3 160 S4 S6 PCH PCL S5 PD SET CYCLE PORT DATA PCH PORT DATA PCL S2 M1 or M2 S1 FLOATING FLOATING FLOATING FLOATING *ALF=“1” SOFT POWER DOWN MODE PORT DATA M1 MSM80C154S/83C154S/85C154HVS Figure 4-63 Soft power down mode setting and I/O floating time chart (external ROM mode)
INTERNAL SPECIFICATIONS 4.8.4 Hard power down mode (HPD) setting To set hard power down mode (HPD), “1” is set in bit 6 (HPD) of the power control register (PCON 87H) in advance to attain the circuit connections shown in Figure 4-61. Hard power down mode is set when the level of the power failure detect signal applied to the HPDI pin (bit 5 of port 3) is changed from level “1” to level “0”. XTAL1·2 operations are stopped in this mode.
162 Figure 4-64 Hard power down mode equivalent circuit CPU CLOCK XTAL 1 HPDI CONTROL I/O FLOATING PCON 87H Bit SMOD HPD RPD — GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 Set • • IOCON 0F8H Bit Set — T32 SERR IZC P3HZ P2HZ P1HZ ALF 7 6 5 4 3 2 1 0 • MSM80C154S/83C154S/85C154HVS XTAL 2
INTERNAL SPECIFICATIONS Table 4-26 CPU pin details (ALF=0) in hard power down mode (HPD) Name Internal ROM External ROM P1.0/T2 Port data output Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.3 Port data output Port data output P1.4 Port data output Port data output P1.5 Port data output Port data output P1.6 Port data output Port data output P1.7 Port data output Port data output RESET “0” level input “0” level input P3.
164 PORT DATA PORT DATA 1 0 1 0 PORT 2 PORT 3 S5 HPD SET CYCLE PORT DATA 1 0 PCON-bit 6 1 0 1 0 *HPDI [P3.
165 HPD SET CYCLE M1 PORT DATA PORT DATA PORT DATA FLOATING *ALF=“0” HARD POWER DOWN MODE PORT DATA 1 0 PCH PORT 3 PCH PORT DATA PCH PCL S1 1 0 PCL S6 PORT 2 1 0 PCON-bit 6 S5 PORT DATA 1 0 *HPDI [P3.
MSM80C154S/83C154S/85C154HVS Table 4-27 CPU pin details (ALF=1) in hard power down mode (HPD) Name Internal ROM External ROM P1.0/T2 Floating Floating P1.1/T2EX Floating Floating P1.2 Floating Floating P1.3 Floating Floating P1.4 Floating Floating P1.5 Floating Floating P1.6 Floating Floating P1.7 Floating Floating RESET “0” level input “0” level input P3.0/RXD Floating Floating P3.1/TXD Floating Floating P3.2/ INT0 External data input External data input P3.
167 PORT DATA PORT DATA 1 0 1 0 PORT 2 PORT 3 S4 S5 HPD SET CYCLE PORT DATA 1 0 PCON-bit 6 1 0 1 0 *HPDI [P3.
1 0 1 0 PORT 3 1 0 PCON-bit 6 PORT 2 1 0 *HPDI [P3.
INTERNAL SPECIFICATIONS 4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation) 4.9.1 Outline CPU power down mode (IDLE, PD, and HPD) can be cancelled (CPU activation) in the following two ways. The CPU is reset when a “1” reset signal is applied to the CPU RESET pin, and the program is executed from address 0. This method can be used in IDLE, PD, and HPD modes.
1 0 1 0 1 0 1 0 ALE PSEN PCON-bit 0 *RESET S3 S4 170 PORT DATA PORT DATA 1 0 1 0 1 0 PORT 1 PORT 2 PORT 3 S5 IDLE MODE RESET CYCLE PORT DATA 1 0 PORT DATA S2 PORT 0 CPU RESET 1 CONTROL 0 1 0 XTAL1 S1 M1 → M2 S6 S1 S4 FLOATING S3 S5 PORT DATA=1 PORT DATA=1 PORT DATA=1 S2 M1 → M2 S6 S1 S2 S3 M1 S4 S5 S6 S2 S3 S4 EXECUTE CYCLE S1 M1 S5 S6 MSM80C154S/83C154S/85C154HVS Figure 4-69 Restart from idle mode by reset (internal ROM mode)
1 0 1 0 1 0 ALE PSEN *RESET 171 PCH PORT DATA 1 0 1 0 PORT 2 PORT 3 S4 IDLE MODE PORT DATA 1 0 S3 PORT 1 S2 1 0 1 0 S1 PORT 0 PCON-bit 0 CPU RESET 1 CONTROL 0 1 0 XTAL1 S6 M1 S5 S6 S1 S4 FLOATING S3 S5 S6 S1 RESET CYCLE PORT DATA=1 PORT DATA=1 PORT DATA=1 S2 M1 → M2 S2 S3 M1 S4 S1 S4 PCH S3 PCL S2 EXECUTE CYCLE PCH S6 PCL S5 M1 S6 PCH PCL S5 INTERNAL SPECIFICATIONS Figure 4-70 Restart from idle mode by reset (external ROM mode)
1 0 1 0 1 0 1 0 ALE PSEN PCON-bit 1 *RESET S3 S4 172 PORT DATA PORT DATA 1 0 1 0 1 0 PORT 1 PORT 2 PORT 3 S5 S6 S1 SOFT POWER DOWN MODE RESET CYCLE PORT DATA 1 0 PORT DATA S2 PORT 0 CPU RESET 1 CONTROL 0 1 0 XTAL1 S1 M1 → M2 S4 FLOATING S3 S5 PORT DATA=1 PORT DATA=1 PORT DATA=1 S2 M1 → M2 S6 S1 S2 S3 M1 S4 S5 S6 S2 S3 S4 EXECUTE CYCLE S1 M1 S5 S6 MSM80C154S/83C154S/85C154HVS Figure 4-71 Restart from soft power mode by reset (internal ROM mode)
1 0 1 0 1 0 1 0 ALE PSEN PCON-bit 1 *RESET 173 PORT DATA PORT DATA 1 0 1 0 PORT 2 PORT 3 S5 S6 S1 SOFT POWER DOWN MODE RESET CYCLE PORT DATA 1 0 S4 PORT 1 S3 1 0 S2 PORT 0 CPU RESET 1 CONTROL 0 1 0 XTAL1 S1 M1 → M2 S4 FLOATING S3 S5 PORT DATA=1 PORT DATA=1 PORT DATA=1 S2 M1 → M2 S6 S1 S2 S3 M1 S4 S1 S4 PCH S3 PCL S2 EXECUTE CYCLE PCH S6 PCL S5 M1 S6 PCH PCL S5 INTERNAL SPECIFICATIONS Figure 4-72 Restart from soft power mode by reset (external ROM mo
1 0 1 0 1 0 1 0 1 0 ALE PSEN IOCON-bit 0 HPDI[P3.
1 0 1 0 1 0 1 0 1 0 ALE PSEN IOCON-bit 0 HPDI[P3.
MSM80C154S/83C154S/85C154HVS 4.9.3 Cancellation of CPU power down mode (IDLE, PD) by interrupt signal When idle mode (IDLE) and soft power down mode (PD) are cancelled by interrupt signal, power down mode cancellation condition is determined by bit 5 (RPD) of the power control register (PCON 87H) shown in Table 4-29. When RPD is “0”, power down mode can be cancelled by interrupt signal and CPU executes program from the interrupt address only when the CPU has been set to interrupt enable status.
INTERNAL SPECIFICATIONS IE0 [TCON.1] IE.0 TF0 [TCON.5] IE.1 IE1 [TCON.3] IE.2 IDLE, PD MODE INTERRUPT & RESTART TF1 [TCON.7] IE.3 RI/TI [SCON.0, 1] IE.4 EXF2/TF2[T2CON.6, 7] IE.5 IE.
S4 S6 S1 PORT DATA 1 0 PORT DATA S5 WASTE CYCLE S3 PORT 3 IDLE MODE S2 PORT DATA S1 1 0 S6 PORT 2 1 0 PCON-bit 0 S5 PORT DATA 1 0 IE0 or IE1 OUT S4 1 0 1 0 *INT0 or INT1 S3 PORT 1 1 0 PSEN S2 1 0 1 0 ALE S1 M1 PORT 0 1 0 XTAL1 S6 M1 S2 S3 M1 S4 S6 S1 S2 S3 S4 INTERRUPT EXECUTE CYCLE S5 M2 S5 S6 MSM80C154S/83C154S/85C154HVS Figure 4-76 Restart from idle mode by interrupt INT0 or 1 (internal ROM mode) 178
1 0 1 0 PORT 3 1 0 PCON-bit 0 PORT 2 1 0 IE0 or IE1 OUT 1 0 1 0 *INT0 or INT1 PORT 1 1 0 PSEN 1 0 1 0 ALE PORT 0 1 0 XTAL1 S6 S1 179 S4 FLOATING S3 IDLE MODE S2 M1 S5 S1 PCH S6 S3 S4 S6 S1 PORT DATA PORT DATA PCL S5 WASTE CYCLE S2 M1 S4 PCH S3 PCL S2 M1 S1 S4 PCH S3 PCL S2 INTERRUPT EXECUTE CYCLE PCH S6 PCL S5 M2 S6 PCH PCL S5 INTERNAL SPECIFICATIONS Figure 4-77 Restart from idle mode by interrupt INT0 or 1 (external ROM mode)
WASTE CYCLE 180 SOFT POWER DOWN MODE S5 S6 S1 S2 S3 M2 INTERRUPT EXECUTE CYCLE PORT DATA 1 0 PORT 3 S4 PORT DATA S3 1 0 S2 PORT 2 S1 PORT DATA 1 0 PCON-bit 1 S6 1 0 1 0 IE0 or IE1 OUT S5 PORT 1 1 0 *INT0 or INT1 S4 PORT DATA 1 0 PSEN S3 1 0 1 0 ALE S2 M1 PORT 0 1 0 XTAL1 S1 M1 S4 S5 S6 S1 S3 S4 S5 EXECUTE CYCLE S2 M1 S6 MSM80C154S/83C154S/85C154HVS Figure 4-78 Restart from soft power down mode by Interrupt INT0 or 1 (internal ROM mode)
1 0 1 0 PORT 3 1 0 PCON-bit 1 PORT 2 1 0 IE0 or IE1 OUT 1 0 1 0 *INT0 or INT1 PORT 1 1 0 PSEN 1 0 1 0 ALE PORT 0 1 0 XTAL1 181 S3 S4 S1 PCH S6 PCL S5 WASTE CYCLE PCH S2 SOFT POWER DOWN MODE S1 M1 S3 S4 S1 PCH S6 PCL S5 S4 PCH S3 PCL S2 M2 INTERRUPT EXECUTE CYCLE PORT DATA PCH PORT DATA PCL S2 M1 S1 PCH S6 PCL S5 S4 S6 PCH PCL S5 EXECUTE CYCLE PCH S3 PCL S2 M1 INTERNAL SPECIFICATIONS Figure 4-79 Restart from soft power down mode by interrup
MSM80C154S/83C154S/85C154HVS 4.9.3.2 Cancellation of CPU power down mode (IDLE, PD) by interrupt request signal and restart from next address of stop address To cancel idle mode (IDLE) or soft power down mode (PD) by interrupt request signal and then resume execution from the next address after the stop address, “1” is set in bit 5 (RPD) of the power control register.
S4 S5 S1 PORT DATA 1 0 WASTE CYCLE S6 PORT DATA LEVEL SENSE S3 PORT 3 IDLE MODE S2 PORT DATA S1 1 0 PCON-bit 0 S6 PORT 2 1 0 S5 PORT DATA 1 0 IE0 or IE1 OUT S4 1 0 1 0 *INT0 or INT1 S3 PORT 1 1 0 PSEN S2 1 0 1 0 ALE S1 M1 PORT 0 1 0 XTAL1 S6 M1 S3 S4 EDGE SENSE S2 M1 S6 S1 S2 S3 S4 INTERRUPT EXECUTE CYCLE S5 M2 S5 S6 INTERNAL SPECIFICATIONS Figure 4-81 Restart from idle mode by INT0 or 1 (internal ROM mode) 183
1 0 PORT 3 PCON-bit 0 1 0 1 0 PORT 2 1 0 *IE0 or IE1 OUT 1 0 1 0 INT0 or INT1 PORT 1 1 0 PSEN 1 0 1 0 ALE PORT 0 1 0 XTAL1 S6 S1 184 S4 FLOATING S3 IDLE MODE S2 M1 S5 S1 PCH S6 S4 S5 S6 S1 PORT DATA PORT DATA PCL LEVEL SENSE S3 WASTE CYCLE S2 M1 S3 S4 PCL PCH EDGE SENSE S2 M1 S1 S4 PCH S3 PCL S2 INTERRUPT EXECUTE CYCLE PCH S6 PCL S5 M2 S6 PCH PCL S5 MSM80C154S/83C154S/85C154HVS Figure 4-82 Restart from idle mode by INT0 or 1 (external ROM mode
185 FLOATING 1 0 PORT 3 SOFT POWER DOWN MODE FLOATING 1 0 PORT 2 PCON-bit 1 FLOATING 1 0 1 0 1 0 IE0 or IE1 OUT PORT 1 1 0 INT0 or INT1 FLOATING 1 0 PSEN 1 0 1 0 ALE PORT 0 1 0 XTAL1 S1 S3 S4 S5 WASTE CYCLE S2 M1 S6 S3 S4 LEVEL SENSE S2 S5 EXECUTE CYCLE PORT DATA PORT DATA PORT DATA PORT DATA S1 M1 S6 S2 S3 S4 S5 EXECUTE CYCLE EDGE SENSE S1 M1 S6 INTERNAL SPECIFICATIONS Figure 4-83 Restart from soft power down mode by INT0 or 1 (internal ROM mode)
186 FLOATING 1 0 PORT 3 SOFT POWER DOWN MODE FLOATING 1 0 PORT 2 PCON-bit 1 FLOATING 1 0 1 0 1 0 IE0 or IE1 OUT PORT 1 1 0 *INT0 or INT1 FLOATING 1 0 PSEN 1 0 1 0 ALE PORT 0 1 0 XTAL1 S1 S3 S4 S3 M1 S4 PCL LEVEL SENSE S2 S2 S3 M1 PCH S4 S6 PCH PCL S5 EXECUTE CYCLE PCL EDGE SENSE S1 PCH S6 PCL S5 EXECUTE CYCLE PORT DATA PCH PORT DATA S1 PCH S6 PCL S5 WASTE CYCLE PORT DATA S2 M1 MSM80C154S/83C154S/85C154HVS Figure 4-84 Restart from soft power do
INTERNAL SPECIFICATIONS 4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode Figures 4-85-1/2 and 2/2 show the examples of the MSM80C154S/83C154S battery backup circuits with hard power down mode. The hard power down mode serves to retain data stored in the CPU and external RAM if the AC 100V power failure occurs. Figure 4-85-1/2 shows the CPU, power failure detector, and external RAM control unit. Figure 4-85-2/2 shows the external RAM.
VR 0.1µF 3 8 5 ICL3211 43K 20K 18K 4 5.1K A 5V 2.2V B 5.1K AC100V + – 1000µF + – 10PF 5.1K 10µF P0.6 P0.7 ALE P0.6 P0.7 ALE EA P2.7 P2.6 P2.5 P2.4 Figure 4-85-1/2 MSM80C154S/83C154S battery back up with hard power down mode 5.1K 200K 74HC08 74HC02 74HC02 T1(P3.5) RESET VSS P2.3 C GND ACC P2.7 I/O control signal C B G1 P2.5 P2.4 P2.3 A G2B G2A SN7408 SN7408 P2.6 P2.2 P0.5 P0.5 P2.2 P0.4 P0.4 P2.1 P0.3 P0.3 P2.0 P0.2 P0.2 P2.1 P0.1 P0.1 P2.
189 L ALE OE WR D7 D6 D5 D4 D3 D2 D1 D0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P2.0 P2.1 P2.2 VCA CS0 CS7 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 VCC GND SN74LS373 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 MSM5128RS D0 D1 D2 D3 D4 D5 D6 D7 MSM5128RS D0 D1 D2 D3 D4 D5 D6 D7 1k ×8 VSS VCC VSS VCC 51K 51K 51K CS WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9A10 CS CS WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9A10 CS 0.1µF 0.
MSM80C154S/83C154S/85C154HVS 5.
INPUT/OUTPUT PORTS 191
MSM80C154S/83C154S/85C154HVS 5. INPUT/OUTPUT PORTS 5.1 Outline MSM80C154S/MSM83C154S is equipped with four 8-bit input/output ports. The functions of these four ports (port 0, 1, 2, and 3) are listed below. 1) Port 0: Input/output bus port, address output port, and data input/output port. 2) Port 1: Quasi-bidirectional input/output port and control input pin. 3) Port 2: Quasi-bidirectional input/output port and address output port.
INPUT/OUTPUT PORTS INTERNAL BUS PORT 0 READ D Q N WPO MODIFY Figure 5-2 Port 0 input/Output port equivalent circuit in internal ROM mode INTERNAL BUS VCC PC0~7 RA0~7 ACC0~7 P PORT 0 N READ Figure 5-3 Port 0 equivalent circuit during address and data input/output in external ROM/RAM mode 193
MSM80C154S/83C154S/85C154HVS Table 5-1 Port 0 pin table PORT0 Accumulator bit 1 P0.0 ACC.0 PC –0 RA 2 P0.1 ACC.1 PC –1 RA 3 P0.2 ACC.2 PC –2 RA 4 P0.3 ACC.3 PC –3 RA 5 P0.4 ACC.4 PC –4 RA 6 P0.5 ACC.5 PC –5 RA 7 P0.6 ACC.6 PC –6 RA 8 P0.7 ACC.
INPUT/OUTPUT PORTS 5.3 Port 1 Port 1 is a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-4. A “quasi-bidirectional port” refers to a port which has internal pull-up resistance when used as an input port. The internal equivalent circuit is shown in Figure 5-5. If a quasi-bidirectional port is used exclusively as an output port, the port output driver becomes a totem-pole type for driving “1” and “0” data.
MSM80C154S/83C154S/85C154HVS INTERNAL BUS VCC CONTROL D C Q P1 P2 P3 MODIFY PORT 1 READ D WP1 Q N Figure 5-4 Port 1 internal equivalent circuit 196
INPUT/OUTPUT PORTS VCC . R=500Ω . ON . R=10kΩ . P1 ON . R=100kΩ . P2 ON VCC IOH . R=500Ω . OFF . R=10kΩ . P1 ON . R=100kΩ . P2 ON P3 P3 INTERNAL BUS INTERNAL BUS READ OFF READ N (A) When accelerator circuit is activated VCC . R=500Ω . OFF . R=10kΩ . P1 OFF . R=100kΩ .
MSM80C154S/83C154S/85C154HVS M1 S6 XTAL1 10- ALE 10- PSEN 1 0 W-PORT S1 S2 S3 M1 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 10 CPU-BUS 1 0 PORT-OUT 10 *P1·2·3TR-ON 10 PORT DATA="0" PORT DATA="1" * Figure 5-6 Quasi-bidirectional port accelerator circuit operation time chart 198 S2
INPUT/OUTPUT PORTS VCC . R=100kΩ . . R=10kΩ . ON P2 ON P3 INTERNAL BUS READ OFF N (A) "1" data writing equivalent circuit VCC VCC . R=100kΩ . . R=10kΩ . ON P2 IIH ON P3 ON 10kΩ INTERNAL BUS READ OFF OFF N (B) "1" data input equivalent circuit VCC VCC . R=100kΩ . ON P3 . R=10kΩ .
MSM80C154S/83C154S/85C154HVS Table 5-2 Port 1 CPU control pin table PORT1 Function P1.0 T2 [TIMER COUNTER 2 EXTERNAL CLOCK] P1.1 T2EX [TIMER COUNTER 2 EXTERNAL CONTROL] Table 5-3 Port 1 pin table PORT1 Accumulator bit 1 P1.0 ACC.0 2 P1.1 ACC.1 3 P1.2 ACC.2 4 P1.3 ACC.3 5 P1.4 ACC.4 6 P1.5 ACC.5 7 P1.6 ACC.6 8 P1.7 ACC.
INPUT/OUTPUT PORTS 5.4 Port 2 Port 2 can function as a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-8. It can also be used for output of addresses 8 thru 15 in external ROM and external RAM (using DPTR) modes. When port 2 is used as a quasi-bidirectional port, it functions in much the same way as port 1.
MSM80C154S/83C154S/85C154HVS VCC PC/DATA P1 P2 P3 PC8~15 RA8~15 (DPH) PORT 2 N Figure 5-9 Port 2 address output equivalent circuit for external memory Table 5-4 Port 2 pin table PORT2 Accumulator bit 1 P2.0 ACC.0 PC –8 RA 2 P2.1 ACC.1 PC –9 RA 3 P2.2 ACC.2 PC –10 RA 4 P2.3 ACC.3 PC –11 RA 5 P2.4 ACC.4 PC –12 RA 6 P2.5 ACC.5 PC –13 RA 7 P2.6 ACC.6 PC –14 RA 8 P2.7 ACC.
INPUT/OUTPUT PORTS 5.5 Port 3 Port 3 can function as a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-10, and can also be used as a CPU control pin. When port 3 is used as a quasi-bidirectional port, all functions are identical to those described for port 1. And when used as a CPU control pin, the port is used after first setting “1” data in the port latch.
MSM80C154S/83C154S/85C154HVS Table 5-5 Port 3 CPU control pin function table PORT3 PORT 3 PIN ALTERNATE FUNCTION P3.0 RXD [SERIAL INPUT PORT] P3.1 TXD [SERIAL OUTPUT PORT] P3.2 INT0 [EXTERNAL INTERRUPT 0] P3.3 INT1 [EXTERNAL INTERRUPT 1] P3.4 T0 [TIMER/COUNTER 0 CLOCK] T1 [TIMER/COUNTER 1 CLOCK] P3.5 HPDI [HARD POWER DOWN INPUT] P3.6 WR [EXTERNAL DATA MEMORY WRITE STROBE] P3.7 RD [EXTERNAL DATA MEMORY READ STROBE] Table 5-6 Port 3 pin table PORT3 Control Accumulator bit 1 P3.
INPUT/OUTPUT PORTS 5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD) The port 0, 1, 2, and 3 output status can be set to either data output or floating when MSM80C154S/MSM83C154S is in power down mode (PD, HPD). To set these ports to output status in power down mode, bit 0 (ALF) of the I/O control register (IOCON 0F8H) is reset to “0” before PD or HPD mode is activated (see Figure 5-11).
MSM80C154S/83C154S/85C154HVS MODIFY PORT1, 2, 3 VCC D P2-10kΩ P3-100kΩ Q W PORT I/O READ N INTERNAL BUS POWER DOWN [IOCON 0F8H] Bit 7 6 5 4 3 2 1 0 Flag — T32 SERR IZC P3HZ P2HZ P1HZ ALF • • • • • Set Figure 5-11 Control circuit for ports 0, 1, 2, 3 by lOCON 206
INPUT/OUTPUT PORTS 5.7 High Impedance Input Port Setting of Each Ouasi-bidirectional Port 1, 2, and 3 Each of the quasi-bidirectional input ports 1, 2, and 3 can be set as high impedance input ports. This high impedance condition is achieved by setting “1” in bits 1 (P1HZ), 2 (P2HZ), and 3 (P3HZ) of the I/O control register (IOCON 0F8H) shown in Figure 5-11. Port 1 is set by P1HZ, port 2 by P2HZ, and port 3 by P3HZ.
MSM80C154S/83C154S/85C154HVS 5.9 Precautions When Driving External Transistors by Ouasi-bidirectional Port Output Signals The following points must be carefully considered when quasi-bidirectional ports are used to drive a transistor by the circuit shown in Figure 5-12. Even though the CPU output in this circuit is at “1” level, the port output pin level may be clamped by the base-emitter voltage VBE (0.7V) of an external NPN transistor, resulting in a pin level of “0”.
INPUT/OUTPUT PORTS VCC VCC 10kΩ 100kΩ OUT P IB CPU "1" OUT Figure 5-13 Drive circuit for NPN transistor by level shifter VCC CPU "0" OUT OUT IB Figure 5-14 PNP transistor direct connection drive circuit 209
MSM80C154S/83C154S/85C154HVS 5.
INPUT/OUTPUT PORTS 2) Two machine cycle instruction output timing M2 S1 XTAL1 1 0 ALE 1 0 S2 S3 M1 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 2M CYCLE OP W-PORT 1 0 PORT-OUT 1 0 PORT OLD DATA PORT NEW DATA MOV data address, # data MOV data address 1, data address 2 ORL data address, # data MOV bit address, C ANL data address, # data XRL data address, # data JBC bit address, code address POP data address MOV data address, @Rr MOV data address, Rr Figure 5-16 Two machine cycle instruction port
MSM80C154S/83C154S/85C154HVS 5.11 Port Data Manipulating Instructions The MSM80C154S/MSM83C154S port operation instructions for ports 0, 1, 2, and 3 are divided into two groups-one where external signals applied to the port pin are used according to the instruction to be used, and the other where port latch data uneffected by the external signals is used. Instructions which use port latch data are listed below.
INPUT/OUTPUT PORTS 213
MSM80C154/83C154/85C154 6.
ELECTRICAL CHARACTERISTICS 215
MSM80C154/83C154/85C154 6. ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Parameter Symbol Conditions VCC VI Tstg Rating Unit Ta=25°C –0.5~7 V Ta=25°C –0.5~VCC+0.5 V — –55~+150 °C Symbol Conditions Rating Unit VCC See below 2.0~6 V 2~6 V Supply voltage Input voltage Storage temperature 6.
ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics 1 (VCC=4.0 to 6.0V,VSS=0V, Ta=–40°C to +85°C) Parameter Input Low Voltage Symbol Conditions Min Typ Max Unit VIL — –0.5 — 0.2VCC V Measuring Circuit –0.1 Input High Voltage VIH Except XTAL1, EA and RESET Input High Voltage VIH1 — VCC+0.5 V 0.7VCC — VCC+0.5 V 0.2VCC +0.9 XTAL1 and EA RESET Output Low Voltage VOL IOL=1.6mA — — 0.45 V VOL1 IOL=3.2mA — — 0.45 V IOH=–60µA 2.4 — — V IOH=–30µA 0.
MSM80C154/83C154/85C154 Maximum Power Supply Current Normal Operation ICC (mA) 4V 5V 6V 1MHz 2.2 3.1 4.1 3MHz 3.7 5.2 7.0 12MHz 12.0 16.0 20.0 16MHz 16.0 20.0 25.0 20MHz 19.0 25.0 30.0 VCC 4.5V 5V 6V 25.0 29.0 35.0 VCC Freq. Freq. 24MHz Maximum Power Supply Current Idle Mode ICC (mA) 4V 5V 6V 1MHz 0.8 1.2 1.6 VCC Freq. 3MHz 1.2 1.7 2.3 12MHz 3.1 4.4 5.9 16MHz 3.8 5.5 7.3 20MHz 4.5 6.4 8.6 VCC 4.5V 5V 6V 6.4 7.4 9.8 Freq.
ELECTRICAL CHARACTERISTICS DC Characteristics 2 Parameter Input Low Voltage (VCC=2.2 to 4.0 V, VSS=0 V, Ta=-40 to +85°C) MeasMin. Typ. Max. Unit uring circuit Condition Symbol VIL — Except XTAL1, EA, –0.5 — 0.25 VCC–0.1 V Input High Voltage VIH 0.25 VCC+0.9 — VCC+0.5 V Input High Voltage VIH1 XTAL1, RESET, and EA 0.6 VCC+0.6 — VCC+0.
MSM80C154/83C154/85C154 Measuring circuits Note 3 V A IO V VCC INPUT VIL Note 1 Note 2 OUTPUT VIH INPUT VCC 2 A VSS VSS 3 4 OUTPUT 1 Note 2 VCC VIH V VIL A VSS Note 3 INPUT OUTPUT VIL Note 3 INPUT VCC VIH VSS Note 1 : Repeated for specified input pins. 2 : Repeated for specified output pins. 3 : Input logic for specified status.
ELECTRICAL CHARACTERISTICS 6.4 External Program Memory Access AC Characteristics VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load Variable clock from*1 Parameter Symble Unit 1 to 24 MHz Min. Max. XTAL1, XTAL 2 Oscillation Cycle tCLCL 41.
MSM80C154/83C154/85C154 External program memory read cycle tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tPXAV tPXIZ tLLAX tAZPL PORT 0 A0~A7 tPXIX INSTR IN A0~A7 tAVIV PORT 2 A8~A15 A8~A15 222 A0~A7
ELECTRICAL CHARACTERISTICS 6.5 External Data Memory Access AC Characteristics VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load Variable clock from*1 Parameter Symbol Unit 1 to 24 MHz Min. Max. XTAL1, XTAL2 Oscillator Cycle tCLCL 45.
MSM80C154/83C154/85C154 External data memory read cycle tLHLL tWHLH ALE PSEN tLLDV tLLWL tRLRH RD tRHDZ tAVLL tLLAX tRLDV tRHDX tAZRL PORT 0 INSTR IN A0~A7 RrorDPL A0~A7 PCL A0~A7 PCL DATA IN tAVWL tAVDV PORT 2 PCH A8~A15 PCH P2.0~P2.7 DATA or A8~A15 PCH A8~A15 PCH External data memory write cycle tLHLL tWHLH ALE PSEN tLLWL tWLWH WR tLLAX tQVWH tAVLL tWHQX tQVWX PORT 0 INSTR IN A0~A7 PCL A0~A7 RrorDPL DATA IN A0~A7 PCL tAVWL PORT 2 A8~A15 PCH A8~A15 PCH P2.0~P2.
ELECTRICAL CHARACTERISTICS 6.6 Serial Port (I/O Extension Mode) AC Characteristics VCC=2.2 to.
MSM80C154/83C154/85C154 MACHINE CYCLE ALE tXLXL 226 SHIFT CLOCK tQVXH tXHQX OUTPUT DATA tXHDV INPUT DATA VALID tXHDX VALID VALID VALID VALID VALID VALID VALID
ELECTRICAL CHARACTERISTICS 6.7 AC Characteristics Measuring Conditions 1. Input/output signal VOH VIH VIL VOH VIH TEST POINT VIL VOL VOL * The input signals in AC test mode are either VOH (logic “1”) orVOL (logic “0”). Timing measurements are made atVIH (logic “1”) and VIL (10gic “0”). 2. Floating Floating VOH VIH VIH VIL VIL VOL VOH VOL * The port 0 floating interval is measured from the time the port 0 pin Voltage drops below VIH after sinking to GND at 2.
MSM80C154/83C154/85C154 6.8 XTAL1 External Clock Input Waveform Conditions Parameter Symbol Min Max Unit Oscillator Freq. 1/tCLCL 0 24 MHz High Time tCHCX 15 — ns Low Time tCLCX 15 — ns Rise Time tCLCH — 5 ns Fall Time tCHCL — 5 ns EXTERMINAL OSCILLATOR SIGNAL tCHCX tCHCX 0.7VCC 0.2VCC–0.1 tCLCH tCHCL tCLCL EXTERMINAL OSCILLATOR SIGNAL NC XTAL2 XTAL1 VSS 228 VCC–0.5 0.
7.
MSM80C154S/83C154S/85C154HVS 230
DESCRIPTION OF INSTRUCTIONS 7. DESCRIPTION OF INSTRUCTIONS 7.1 Outline MSM80C154S/MSM83C154S is a microcontroller designed for parallel processing in an 8-bit ALU. The instructions consist of 8-bit units of data, and are available as 1-word 1 machine, 2-machine, and 4-machine cycle instructions as well as 2-word 1-machine and 2-machine cycle instructions and 3-word 2-machine cycle instructions. There is a total of 112 instructions classified into the following groups.
MSM80C154S/83C154S/85C154HVS 7.2 Description of Instruction Symbols The instruction symbols have the following meanings. A AB AC B C DPTR PC Rr SP AND OR XOR + – × / (X) ((X)) # @ = ≠ ← → — < > bit address code address data relative offset direct address Accumulator Register pair Auxiliary carry Arithmetic operation register Carry (the bit 7 carry represented by CY is changed to C in Chapter 7.
0 L 233 0 1 2 4 DEC A ACALL LCALL address 11 RRC A address 16 (Page 0) RL A RLC A ORL direct , #data ANL direct , #data XRL direct , #data JMP AJMP address 11 RET (Page 1) ACALL address 11 RETI (Page 1) AJMP ORL address 11 direct, A (Page 2) ACALL ANL address 11 direct, A (Page 2) AJMP XRL address 11 direct, A (Page 3) ACALL ORL C, address 11 bit (Page 3) JBC bit, JB bit, JNB bit, JC bit, JNC rel JZ rel 5 6 7 8 direct 1101 AJMP MOVX A, address 11 @R0 (Page 7) MOVX @R1, A
A, Rr ADD A, direct ADD A, @Rr ADD A, #data ADDC A, Rr ADDC A, direct 234 Arithmetic operation instructions ADDC A, @Rr ADDC A, #data SUBB A, Rr SUBB A, direct SUBB A, @Rr SUBB A, #data 0 0 1 0 1 r2 r1 r0 0 0 1 0 0 1 0 1 a7 a6 a5 a4 a3 a2 a1 a0 0 0 1 0 0 1 1 r 0 0 1 0 0 1 0 0 I7 I6 I5 I4 I3 I2 I1 I0 0 0 1 1 1 r2 r1 r0 0 0 1 1 0 1 0 1 a7 a6 a5 a4 a3 a2 a1 a0 0 0 1 1 0 1 1 r 0 0 1 1 0 1 0 0 I7 I6 I5 I4 I3 I2 I1 I0 1 0 0 1 1 r2 r1 r0 1
Classification Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description Page CLR A 1 1 1 0 0 1 0 0 1 1 (A)←0 272 CPL A 1 1 1 1 0 1 0 0 1 1 (A)←(A) 275 RL A 0 0 1 0 0 0 1 1 1 1 349 C Accumulator ← ← ← ← ← ← ← ← 7 235 A 0 0 1 1 0 0 1 1 1 350 1 C Accumulator ← ← ← ← ← ← ← ← 7 RR A 0 0 0 0 0 0 1 1 1 351 1 C Accumulator ← ← ← ← ← ← ← ← 7 RRC A 0 0 0 1 0 0 1 1 1 352 Accumulator ← ← ← ← ← ← ← ← 7 1 1 0 0 0
Mnemonic Increment & decrement instructions INC A INC Rr Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 Page 1 1 (A)←(A)+1 1 1 (Rr)←(Rr)+1 2 1 (direct address)←(direct address)+1 293 289 0 0 0 0 1 r2 r1 r0 0 0 0 0 0 Description 0 0 1 Byte Cycle 1 290 r=0~7 292 INC direct INC @Rr 0 0 0 0 0 1 1 r 1 1 ((Rr))←((Rr))+1 INC DPTR 1 0 1 0 0 0 1 1 1 2 (DPTR)←(DPTR)+1 291 DEC A 0 0 0 1 0 1 0 0 1 1 (A)←(A)–1 281 DEC Rr 0 0
Classification Mnemonic ORL A, #data ORL direct, A Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 0 I7 I6 I5 I4 I3 I2 I1 I0 0 1 0 0 0 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 237 Logical operation instructions 0 1 0 0 0 0 1 Byte Cycle Description Page 2 1 (A)←(A)OR#data 337 2 1 (direct address)←(direct address)OR(A) 344 3 2 (direct address)←(direct address)OR#data 343 1 1 (A)←(A)XOR(Rr) 368 2 1 (A)←(A)XOR(direct address) 369 1 1 (A)←(A)XOR((Rr)) r=0 or 1
Mnemonic Immediate data setting instructions MOV @Rr, #data MOV DPTR, #data Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 1 1 r I7 I6 I5 I4 I3 I2 I1 I0 1 0 0 1 0 0 0 Byte Cycle Description r=0 or 1 Page 311 2 1 ((Rr))←#data 3 2 (DPTR)←#data 319 0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 C 1 1 0 0 0 0 1 1 1 1 (C)←0 273 SETB C 1 1 0 1 0 0 1 1 1 1 (C)←1 353 CPL C 1 0 1 1 0 0 1 1 1 1 (C)←(C) 276 ANL C, bit 1 0 0 0 0
Classification Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Bit manipulation instructions 1 0 1 1 0 0 1 0 Constant value instructions 277 1 1 (A)←(Rr) r=0~7 316 2 1 (A)←(direct address) 317 r 1 1 (A)←((Rr)) r=0 or 1 315 1 1 1 1 1 r2 r1 r0 1 1 (Rr)←(A) r=0~7 321 2 2 (Rr)←(direct address) 2 1 (direct address)←(A) 2 2 (direct address)←(Rr) 3 2 (direct address 1)←(direct address 2) 328 2 2 (direct address)←((Rr)) 325 1 1 ((Rr))←(A) 2 2 ((Rr))←(direct addres
Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Data exchange instructions 1 (A)→ ←(Rr) 2 1 (A)→ ←(direct address) r 1 1 1 r 1 1 0 0 2 2 2 2 2 2 0 0 1 1 r2 r1 r0 1 1 0 0 0 A, Rr XCH A, direct XCH A, @Rr 1 1 0 0 0 1 1 XCHD A, @Rr 1 1 0 1 0 1 1 1 0 0 0 0 PUSH direct POP direct ACALL addr 11 0 1 a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 1 1 0 1 0 0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 A10 A9 A8 1 0 0 Description 1 0 XCH 1 Byte Cycle
Classification Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 RETI 0 1 1 0 0 1 0 Byte Cycle 1 2 Description (PC8~15)←((SP)) Page 348 Subroutine instructions (SP)←(SP)–1 (PC0~7)←((SP)) (SP)←(SP)–1 *INTERRUPT ENABLE AJMP addr 11 A10 A9 A8 0 0 0 1 241 Jump instructions A7 A6 A5 A4 A3 A2 A1 A0 0 LJMP addr 16 0 0 0 0 0 0 1 2 2 3 2 2 2 (PC)←(PC)+2 (PC0~10)←A0~10 255 0 A15 A14 A13 A12 A11 A10 A9 A8 (PC0~15)←A0~15 310 A7 A6 A5 A4 A3 A2 A1 A0 SJMP rel 1 0 0 0 0
Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 CJNE A, #data, rel 1 0 1 1 0 1 0 0 Byte Cycle 3 2 Description 266 (PC)←(PC)+3 I7 I6 I5 I4 I3 I2 I1 I0 IF R7 R6 R5 R4 R3 R2 R1 R0 THEN Page (A)≠#data (PC)←(PC)+relative offset IF (A)<#data 242 Branching instructions THEN (C)←1 ELSE (C)←0 CJNE Rr,#data,rel 1 0 1 1 1 r2 r1 r0 3 2 270 (PC)←(PC)+3 I7 I6 I5 I4 I3 I2 I1 I0 IF R7 R6 R5 R4 R3 R2 R1 R0 THEN (Rr)≠#data r=0~7 (PC)←(PC)+relative offset IF (A)<#data THEN (C)←1 ELS
Classification Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 CJNE @Rr, #data, 1 rel 0 1 1 0 1 1 r Byte Cycle 3 2 Description 264 (PC)←(PC)+3 I7 I6 I5 I4 I3 I2 I1 I0 IF R7 R6 R5 R4 R3 R2 R1 R0 THEN Page ((Rr))≠#data r=0 or 1 (PC)←(PC)+relative offset IF ((Rr))<#data r=0 or 1 THEN (C)←1 ELSE 243 DJNZ Rr, rel 1 1 0 1 1 r2 r1 r0 2 2 R7 R6 R5 R4 R3 R2 R1 R0 285 (PC)←(PC)+2 (Rr)←(Rr)–1 r=0~7 IF r=0~7 (Rr)≠0 THEN (PC)←(PC)+relative offset DJNZ direct, rel 1 1 0 1
Mnemonic JNZ rel Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 0 0 Byte Cycle 2 2 R7 R6 R5 R4 R3 R2 R1 R0 Description (PC)←(PC)+2 IF Page 305 (A)≠0 THEN (PC)←(PC)+relative offset JC rel 0 1 0 0 0 0 0 0 2 2 R7 R6 R5 R4 R3 R2 R1 R0 (PC)←(PC)+2 IF 298 (C)=1 THEN (PC)←(PC)+relative offset JNC rel 0 1 0 1 0 0 0 0 2 2 244 Branching instructions R7 R6 R5 R4 R3 R2 R1 R0 (PC)←(PC)+2 IF 303 (C)=0 THEN (PC)←(PC)+relative offset JB bit, rel 0 0 1 0 0 0 0
Classification Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 Byte Cycle Description External memory instructions MOVX A, @Rr 1 1 1 0 0 0 1 r 1 2 (A)←((Rr)) EXTERNAL RAM MOVX A, @DPTR 1 1 1 0 0 0 0 0 1 2 (A)←((DPTR)) EXTERNAL RAM MOVX @Rr, A 1 1 1 1 0 0 1 r 1 2 ((Rr))←(A) EXTERNAL RAM MOVX @DPTR, A 1 1 1 1 0 0 0 0 1 2 ((DPTR))←(A) EXTERNAL RAM NOP 0 0 0 0 0 0 0 0 1 1 (PC)←(PC)+1 Page r=0 or 1 334 333 r=0 or 1 332 331 336 245 DESCRI
MSM80C154S/83C154S/85C154HVS 7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions Note: “direct address” is represented as “data address” in this detailed description. 1.
DESCRIPTION OF INSTRUCTIONS 2. ADD A, #data (Add immediate data) 7 Instruction code : 0 0 0 1 0 0 1 0 7 I7 #data I6 I5 : (A)←(A)+#data Number of bytes :2 Number of cycles :1 Flags : Description Byte 1 0 Operation (PSW) 0 C AC • • F0 I4 I3 I2 RS1 RS0 OV • I1 I0 F1 P Byte 2 • : An 8-bit immediate data value is added to the accumulator. The result is placed in the accumulator, and the flags are updated.
MSM80C154S/83C154S/85C154HVS 3. ADD A, @Rr (Add indirect address) 7 0 0 Instruction code : Operation : (A)←(A)+((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : (PSW) Description 0 C AC • • 1 F0 0 0 1 RS1 RS0 OV 1 r F1 P • Byte 1 • : The data memory location contents addressed by the register r contents are added to the accumulator. The result is placed in the accumulator, and the flags are updated.
DESCRIPTION OF INSTRUCTIONS 4. ADD A, Rr (Add register) 7 0 Instruction code : Operation : (A)←(A)+(Rr) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : 0 (PSW) Description 0 C AC • • 1 F0 0 1 r2 RS1 RS0 OV r1 r0 F1 P • Byte 1 • : The register r contents are added to the accumulator. The result is placed in the accumulator, and the flags are updated.
MSM80C154S/83C154S/85C154HVS 5. ADD A, data address (Add memory) 7 Instruction code : 0 0 0 1 0 0 1 0 7 a7 Data address a6 a5 a4 a2 a1 a0 RS1 RS0 OV F1 P : (A)←(A)+(data address) Number of bytes :2 Number of cycles :1 Flags : Description Byte 1 0 Operation (PSW) 1 C AC • • F0 a3 • Byte 2 • : The specified data address contents are added to the accumulator. The result is placed in the accumulator, and the flags are updated.
DESCRIPTION OF INSTRUCTIONS 6. ADDC A, #data (Add carry plus immediate data to accumulator) 7 Instruction code : 0 0 0 1 1 0 1 0 7 I7 #data I6 I5 I4 : (A)←(A)+(C)+#data Number of bytes :2 Number of cycles :1 Flags : Description Byte 1 0 Operation (PSW) 0 C AC • • F0 I3 I2 RS1 RS0 OV I1 I0 F1 P • Byte 2 • : The carry flag is added to the accumulator, and an 8-bit immediate data is added to that result.
MSM80C154S/83C154S/85C154HVS 7. ADDC A, @Rr (Add carry plus indirect address to accumulator) 7 0 0 Instruction code : Operation : (A)←(A)+(C)+((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : (PSW) Description 0 C AC • • 1 F0 1 0 1 RS1 RS0 OV 1 r F1 P • Byte 1 • : The carry flag is added to the accumulator, and the contents of data memory location addressed by the register r contents are added to the accumulator.
DESCRIPTION OF INSTRUCTIONS 8. ADD A, Rr (Add carry plus register to accumulator) 7 0 Instruction code : Operation : (A)←(A)+(C)+(Rr) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : 0 (PSW) Description 0 C AC • • 1 F0 1 1 r2 RS1 RS0 OV r1 r0 F1 P • Byte 1 • : The carry flag is added to the accumulator,and the register r contents are added to the result. The result is placed in the accumulator, and the flags are updated.
MSM80C154S/83C154S/85C154HVS 9. ADDC A, data address (Add carry plus memory to accumulator) 7 Instruction code : 0 0 0 1 1 0 1 0 7 a7 Data address a6 a5 a4 a3 a2 a1 a0 RS1 RS0 OV F1 P : (A)←(A)+(C)+(data address) Number of bytes :2 Number of cycles :1 Flags : Description Byte 1 0 Operation (PSW) 1 C AC • • F0 • Byte 2 • : The carry flag is added to the accumulator,and the specified data address contents are added to that result.
DESCRIPTION OF INSTRUCTIONS 10. AJMP code address (Absolute jump within 2K byte page) 7 Instruction code : A10 0 A9 A8 0 0 0 0 7 A7 Call address Byte 1 0 A6 A5 Operations : (PC)←(PC)+2 (PC0~10)←A0~10 Number of bytes :2 Number of cycles :2 Flags : C 1 AC F0 A4 A3 A2 A1 A0 RS1 RS0 OV F1 P Byte 2 (PSW) Description : After an increment ,the program counter PC0~10 is replaced by 11-bit page address data A0~10.
MSM80C154S/83C154S/85C154HVS 11. ANL A, #data (Logical AND immediate data to accumulator) 7 Instruction code : 0 0 1 0 1 0 1 0 7 I7 #data I6 I5 I4 : (A)←(A) AND #data Number of bytes :2 Number of cycles :1 Flags : AC F0 I3 I2 RS1 RS0 OV (PSW) Description Byte 1 0 Operation C 0 I1 I0 F1 P Byte 2 • : The logical AND between an 8-bit immediate data value and the accumulator contents is determined. The result is placed in the accumulator and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 12. ANL A, @Rr (Logical AND indirect address to accumulator) 7 0 0 Instruction code : Operation : (A)←(A) AND ((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : C 1 AC 0 F0 1 0 1 RS1 RS0 OV 1 r F1 P (PSW) Description Byte 1 • : The logical AND between the accumulator contents and the data memory location contents addressed by the register r contents is determined. The result is placed in the accumulator and the flag is updated.
MSM80C154S/83C154S/85C154HVS 13. ANL A, Rr (Logical AND register to accumulator) 7 0 Instruction code : Operation : (A)←(A) AND (Rr) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : 0 C 1 0 AC F0 1 1 r2 RS1 RS0 OV r1 r0 F1 P (PSW) Description Byte 1 • : The logical AND between the accumulator contents and the register r contents is determined. The result is placed in the accumulator and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 14. ANL A, data address (Logical AND memory to accumulator) 7 Instruction code : 0 0 1 0 1 0 1 0 7 a7 Data address a6 a5 a4 a3 a2 a1 a0 RS1 RS0 OV F1 P : (A)←(A) AND (data address) Number of bytes :2 Number of cycles :1 Flags : AC F0 (PSW) Description Byte 1 0 Operation C 1 Byte 2 • : The logical AND between the accumulator contents and the specified data address contents is determined.
MSM80C154S/83C154S/85C154HVS 15. ANL C, bit address (Logical AND bit to carry flag) 7 Instruction code : 0 1 0 0 0 0 0 1 7 b7 Bit address b6 b5 b4 b3 b2 b1 b0 RS1 RS0 OV F1 P : (C)←(C) AND (bit address) Number of bytes :2 Number of cycles :2 Flags : (PSW) Description Byte 1 0 Operation C 0 AC F0 Byte 2 • : The logical AND between the carry flag and the specified bit address contents is determined. The result is placed in the carry flag. Example ANL C, ACC.
DESCRIPTION OF INSTRUCTIONS 16. ANL C,/bit address (Logical AND complement bit to carry flag) 7 Instruction code : 0 1 0 1 1 0 0 0 0 7 b7 Bit address 0 b6 b5 b4 b3 b2 b1 b0 RS1 RS0 OV F1 P Operation : (C)←(C) AND (bit address) Number of bytes :2 Number of cycles :2 Flags : C (PSW) Description Byte 1 AC F0 Byte 2 • : The logical AND between the carry flag and the complement of specified bit address contents is determined. The result is placed in the carry flag.
MSM80C154S/83C154S/85C154HVS 17.
DESCRIPTION OF INSTRUCTIONS 18. ANL data address, A (Logical AND accumulator to memory) 7 Instruction code : 0 0 1 0 1 0 0 1 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 a1 Operation : (data address)←(data address) AND (A) Number of bytes :2 Number of cycles :1 Flags : C 0 AC F0 RS1 RS0 OV F1 a0 Byte 2 P (PSW) Description : The logical AND between the accumulator and the specified data address contents is determined. The result is placed in the specified data address.
MSM80C154S/83C154S/85C154HVS 19.
DESCRIPTION OF INSTRUCTIONS Example CJNE @R1, #05H, TEST LOC OBJ SOURCE 00B4 2155 TEST:AJMP TEST1 0118 B70599 COMP:CJNE @R1, #05H, TEST 011B 020500 OUT:LJMP OUT1 7 Instruction code 0 : 1 0 1 1 0 1 1 1 Byte 1 7 0 0 0 0 0 0 1 0 1 Byte 2 7 0 1 0 0 1 1 0 0 1 Byte 3 Before execution Register 1 After execution Register 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 7 35H 7 35H 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 7 Carry flag 7 Carry flag 0 1 0 0 Program counter Program counter 0 0 0 0 0 0 0 1
MSM80C154S/83C154S/85C154HVS 20.
DESCRIPTION OF INSTRUCTIONS Example CJNE A, #0AH, SS1 LOC OBJ SOURCE 0064 FF SS1:MOV R7, A 00C8 B40599 COMP:CJNE A, #0AH, SS1 00CB 0D INCR:INC R5 7 Instruction code 0 : 1 0 1 1 0 1 0 0 Byte 1 7 0 0 0 0 0 1 0 1 0 Byte 2 7 0 1 0 0 1 1 0 0 1 Byte 3 Before execution Accumulator After execution Accumulator 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 7 Carry flag 7 Carry flag 0 1 0 0 Program counter Program counter 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 15 15 8 7 0
MSM80C154S/83C154S/85C154HVS 21.
DESCRIPTION OF INSTRUCTIONS Example CJNE A, 50H, NEXT LOC OBJ SOURCE 10DC B55044 COMP:CJNE A, 50H, NEXT 10DF 120100 CAL:LCALL TEST 1123 14 NEXT:DEC A 7 Instruction code 0 : 1 0 1 1 0 1 0 1 Byte 1 7 0 0 1 0 1 0 0 0 0 Byte 2 7 0 0 1 0 0 0 1 0 0 Byte 3 Before execution 50H After execution 50H 0 1 0 1 1 1 1 0 0 1 0 1 1 1 1 0 7 Accumulator 7 Accumulator 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 7 Carry flag 7 Carry flag 0 0 0 1 Program counter Program counter 0 0 0 1 0 0 0 0 1 1 0 1 1
MSM80C154S/83C154S/85C154HVS 22.
DESCRIPTION OF INSTRUCTIONS Example CJNE R4, #32H, COUNT LOC OBJ SOURCE 0473 0C COUNT:INC R4 0482 BC32EE COMP:CJNE R4, #32H, COUNT 7 Instruction code 0 : 1 0 1 1 1 1 0 0 Byte 1 7 0 0 0 1 1 0 0 1 0 Byte 2 7 0 1 1 1 0 1 1 1 0 Byte 3 Before execution Register 4 After execution Register 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 7 Carry flag 7 Carry flag 0 1 0 1 Program counter Program counter 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 1 15 15 8 7 0 271 8 7 0
MSM80C154S/83C154S/85C154HVS 23. CLR A (Clear accumulator) 7 Instruction code : 1 Operation : (A)←0 Number of bytes :1 Number of cycles :1 Flags : C 0 1 1 AC F0 0 0 1 RS1 RS0 OV (PSW) Description 0 0 F1 P Byte 1 • : The accumulator is cleared to 0 and flag is updated.
DESCRIPTION OF INSTRUCTIONS 24. CLR C (Clear carry flag) 7 Instruction code : 1 Operation : (C)←0 Number of bytes :1 Number of cycles :1 Flags : C (PSW) Description 0 1 0 AC F0 0 0 0 RS1 RS0 OV 1 1 F1 P • : The carry flag is cleared to 0.
MSM80C154S/83C154S/85C154HVS 25. CLR bit address (Clear bit) 7 Instruction code : 0 1 1 0 0 0 0 1 7 b7 Bit address Byte 1 0 b6 b5 Operation : (bit address)←0 Number of bytes :2 Number of cycles :1 Flags : C 0 AC F0 b4 b3 b2 b1 b0 RS1 RS0 OV F1 P Byte 2 (PSW) Description : The specified bit address content is cleared to 0. Example CLR P1.
DESCRIPTION OF INSTRUCTIONS 26. CPL A (Complement accumulator) 7 1 0 Instruction code : Operation : (A)←(A) Number of bytes :1 Number of cycles :1 Flags : C 1 AC 1 F0 1 0 1 RS1 RS0 OV 0 0 F1 P Byte 1 (PSW) Description : Accumulator data 0 is set to 1 and 1 is set to 0.
MSM80C154S/83C154S/85C154HVS 27. CPL C (Complement carry flag) 7 1 0 Instruction code : Operation : (C)←(C) Number of bytes :1 Number of cycles :1 Flags : C (PSW) Description 0 1 AC F0 1 0 0 RS1 RS0 OV 1 1 F1 P • : The carry flag is set to 1 if 0, set to 0 if 1.
DESCRIPTION OF INSTRUCTIONS 28. CPL bit address (Complement bit) 7 Instruction code : 1 0 0 1 1 0 0 1 7 b7 Bit address Byte 1 0 b6 b5 b4 b3 b2 b1 b0 RS1 RS0 OV F1 P Operation : (bit address)←(bit address) Number of bytes :2 Number of cycles :1 Flags : C 0 AC F0 Byte 2 (PSW) Description : The specified bit address content is set to 1 if 0, and set to 0 if 1. Example CLR B.
MSM80C154S/83C154S/85C154HVS 29. DA A (Decimal adjust accumulator) 7 Instruction code : Operations : 100+6←(AC)=1 or 100>10 101+6 ←(C)=1 or 101>10 (C)←1 Number of bytes :1 Number of cycles :1 Flags : (PSW) Description 1 0 1 0 1 0 1 0 0 F1 P Byte 1 } C AC F0 • RS1 RS0 OV • : The arithmetic operation result located in the accumulator following an addition between two 2-digit decimal number is converted to a normal decimal number.
DESCRIPTION OF INSTRUCTIONS Example DA A 7 Instruction code 0 : 1 1 0 1 0 1 0 0 Byte 1 Before execution Accumulator After execution Accumulator 1 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 7 C AC 7 C AC 0 0 1 0 0 Before execution Accumulator 0 After execution Accumulator 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 1 7 C AC 7 C AC 1 1 1 1 0 Before execution Accumulator 0 After execution Accumulator 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 7 C AC 7 C AC 0 0 1 0 0 279 0
MSM80C154S/83C154S/85C154HVS 30. DEC @Rr (Decrement indirect address) 7 0 Instruction code : Operation : ((Rr))←((Rr))–1 r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : 0 C 0 AC 0 F0 1 0 1 RS1 RS0 OV 1 r F1 P Byte 1 (PSW) Description : The contents of the data memory location addressed by the register r contents are decremented by 1.
DESCRIPTION OF INSTRUCTIONS 31. DEC A (Decrement accumulator) 7 0 Instruction code : Operation : (A)←(A)–1 Number of bytes :1 Number of cycles :1 Flags : 0 C 0 AC 0 F0 1 0 1 RS1 RS0 OV (PSW) Description 0 0 F1 P Byte 1 • : The accumulator contents are decremented by 1, and the flag is updated.
MSM80C154S/83C154S/85C154HVS 32. DEC Rr (Decrement register) 7 0 0 0 0 1 1 Instruction code : Operation : (Rr)←(Rr)–1 r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : C AC F0 r2 RS1 RS0 OV r1 r0 F1 P Byte 1 (PSW) Description : The register r contents are decremented by 1.
DESCRIPTION OF INSTRUCTIONS 33. DEC data address (Decrement memory) 7 Instruction code : 0 0 0 0 1 0 1 0 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 Operation : (data address)←(data address)–1 Number of bytes :2 Number of cycles :1 Flags : C 1 AC F0 RS1 RS0 OV a1 a0 F1 P Byte 2 (PSW) Description : The specified data address contents are decremented by 1.
MSM80C154S/83C154S/85C154HVS 34. DIV AB (Divide accumulator by B) 7 1 0 Instruction code : Operation : (A) quotient←(A)/(B) (B) remainder Number of bytes :1 Number of cycles :4 Flags : C 0 AC 0 F0 0 0 1 RS1 RS0 OV • (PSW) 0 0 F1 P • Byte 1 • : The accumulator contents are devided by the contents of arithmetic operation register (B). The two data values are handled as integers without sign.
DESCRIPTION OF INSTRUCTIONS 35. DJNZ Rr, code address (Decrement register, and jump if not zero) 7 Instruction code : 1 0 1 0 1 1 r2 r1 7 R7 Relative offset Byte 1 0 R6 R5 R4 R3 R2 R1 R0 RS1 RS0 OV F1 P Operations : (PC)←(PC)+2 (Rr)←(Rr)–1 r=0 thru 7 IF (Rr)≠0 THEN (PC)←(PC)+relative offset Number of bytes :2 Number of cycles :2 Flags : C r0 AC F0 Byte 2 (PSW) Description : The register r contents are decremented by 1.
MSM80C154S/83C154S/85C154HVS Example DJNZ R1, LOOP LOC OBJ SOURCE 00FE 2F LOOP:ADD A, R7 010B D9F1 COUNT:DJNZ R1, LOOP 7 Instruction code 0 : 1 1 0 1 1 0 0 1 Byte 1 7 0 1 1 1 1 0 0 0 1 Byte 2 Before execution Register 1 After execution Register 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 7 7 0 Program counter 0 Program counter 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 15 15 8 7 0 286 8 7 0
DESCRIPTION OF INSTRUCTIONS 36.
MSM80C154S/83C154S/85C154HVS Example DJNZ 57H, LOOP 1 LOC OBJ SOURCE 1033 A957 LOOP 1:MOV R1, 57H 1095 D5579B COUNT:DJNZ 57H, LOOP 1 7 Instruction code 0 : 1 1 0 1 0 1 0 1 Byte 1 7 0 0 1 0 1 0 1 1 1 Byte 2 7 0 1 0 0 1 1 0 1 1 Byte 3 Before execution 57H After execution 57H 0 1 1 0 1 0 1 1 7 0 1 1 0 1 0 1 0 0 Program counter 7 0 Program counter 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 15 15 8 7 0 288 8 7 0
DESCRIPTION OF INSTRUCTIONS 37. INC @Rr (Increment indirect address) 7 0 Instruction code : Operation : ((Rr))←((Rr))+1 r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : 0 C 0 AC 0 F0 0 0 1 RS1 RS0 OV 1 r F1 P Byte 1 (PSW) Description : The contents of the data memory location addressed by the register r contents are incremented by 1.
MSM80C154S/83C154S/85C154HVS 38. INC A (Increment accumulator) 7 0 Instruction code : Operation : (A)←(A)+1 Number of bytes :1 Number of cycles :1 Flags : 0 C 0 AC 0 F0 0 0 1 RS1 RS0 OV (PSW) Description 0 0 F1 P Byte 1 • : The accumulator contents are incremented by 1, and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 39. INC DPTR (Increment data pointer) 7 0 Instruction code : Operation : (DPTR)←(DPTR)+1 Number of bytes :1 Number of cycles :2 Flags : 1 C 0 AC 1 0 F0 0 0 RS1 RS0 OV 1 1 F1 P Byte 1 (PSW) Description : 16-bit contents od the data pointer (DPH·DPL) are incremented by 1.
MSM80C154S/83C154S/85C154HVS 40. INC Rr (Increment register) 7 0 0 0 0 0 1 Instruction code : Operation : (Rr)←(Rr)+1 r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : C AC F0 r2 RS1 RS0 OV r1 r0 F1 P Byte 1 (PSW) Description : The register r contents are incremented by 1.
DESCRIPTION OF INSTRUCTIONS 41. INC data address (Increment memory) 7 Instruction code : 0 0 0 0 0 0 1 0 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 Operation : (data address)←(data address)+1 Number of bytes :2 Number of cycles :1 Flags : C 1 AC F0 RS1 RS0 OV a1 a0 F1 P Byte 2 (PSW) Description : The specified data address contents are incremented by 1.
MSM80C154S/83C154S/85C154HVS 42.
DESCRIPTION OF INSTRUCTIONS Example JB 34.3, ENTER LOC OBJ SOURCE 0903 20134A BITTS:JB 34.
MSM80C154S/83C154S/85C154HVS 43.
DESCRIPTION OF INSTRUCTIONS Example JBC 46.1, COUNT 4 LOC OBJ SOURCE 00DC C281 COUNT 4:CLR 128.1 0136 1071A3 BTEST:JBC46.
MSM80C154S/83C154S/85C154HVS 44. JC code address (Jump if carry is set) 7 Instruction code : 0 0 1 0 0 0 0 0 7 R7 Relative offset Byte 1 0 R6 R5 R4 R3 R2 R1 R0 RS1 RS0 OV F1 P Operations : (PC)←(PC)+2 IF (C)=1 THEN (PC)←(PC)+relative offset Number of bytes :2 Number of cycles :2 Flags : C 0 AC F0 Byte 2 (PSW) Description : Control is shifted to a relative jump address if the carry flag is 1.
DESCRIPTION OF INSTRUCTIONS Example JC CARRY LOC OBJ SOURCE 16DC 7110 CHECK:ACALL ADDR 16DE 4015 JMPC:JC CARRY 16F5 07 CARRY:INC @R1 7 Instruction code 0 : 0 1 0 0 0 0 0 0 Byte 1 7 0 0 0 0 1 0 1 0 1 Byte 2 Before execution After execution Carry flag Carry flag 1 1 Program counter Program counter 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 15 15 8 7 0 299 8 7 0
MSM80C154S/83C154S/85C154HVS 45. JMP @A + DPTR (Jump to sum of accumulator and data pointer) 7 0 Instruction code : Operation : (PC)←(A)+(DPTR) Number of bytes :1 Number of cycles :2 Flags : 0 C 1 AC 1 F0 1 0 0 RS1 RS0 OV 1 1 F1 P Byte 1 (PSW) Description : The accumulator contents are added to the data pointer contents, and the resulting sum is placed in the program counter.
DESCRIPTION OF INSTRUCTIONS 46.
MSM80C154S/83C154S/85C154HVS Example JNB 37.3, EXIT LOC OBJ SOURCE 0835 302B22 TEST:JNB 37.
DESCRIPTION OF INSTRUCTIONS 47. JNC code address (Jump if carry is not set) 7 Instruction code : 0 0 1 0 1 0 0 0 7 R7 Relative offset Byte 1 0 R6 R5 R4 R3 R2 R1 R0 RS1 RS0 OV F1 P Operations : (PC)←(PC)+2 IF (C)=0 THEN (PC)←(PC)+relative offset Number of bytes :2 Number of cycles :2 Flags : C 0 AC F0 Byte 2 (PSW) Description : Control is shifted to a relative jump address if the carry flag is 0.
MSM80C154S/83C154S/85C154HVS Example JNC EXIT LOC OBJ SOURCE 0835 5022 TEST:JNC EXIT 0859 85E0F0 EXIT:MOV B, ACC 7 Instruction code 0 : 0 1 0 1 0 0 0 0 Byte 1 7 0 0 0 1 0 0 0 1 0 Byte 2 Before execution After execution Carry flag Carry flag 0 0 Program counter Program counter 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 15 8 7 0 304 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 1 15 8 7 0
DESCRIPTION OF INSTRUCTIONS 48. JNZ code address (Jump if accumulator is not 0) 7 Instruction code : 0 0 1 1 1 0 0 0 7 R7 Relative offset Byte 1 0 R6 R5 R4 R3 R2 R1 R0 RS1 RS0 OV F1 P Operations : (PC)←(PC)+2 IF (A)≠0 THEN (PC)←(PC)+relative offset Number of bytes :2 Number of cycles :2 Flags : C 0 AC F0 Byte 2 (PSW) Description : Control is shifted to a relative jump address if the accumulator contents are not 0.
MSM80C154S/83C154S/85C154HVS Example JNZ TEST LOC OBJ SOURCE 00FC 7030 CHECK:JNZ TEST 012E FB TEST:MOV R3, A 7 Instruction code 0 : 0 1 1 1 0 0 0 0 Byte 1 7 0 0 0 1 1 0 0 0 0 Byte 2 Before execution Accumulator After execution Accumulator 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 7 7 0 Program counter Program counter 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 15 0 8 7 0 306 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 15 8 7 0
DESCRIPTION OF INSTRUCTIONS 49. JZ code address (Jump if accumulator is not 0) 7 Instruction code : 0 0 1 1 0 0 0 0 7 R7 Relative offset Byte 1 0 R6 R5 R4 R3 R2 R1 R0 RS1 RS0 OV F1 P Operations : (PC)←(PC)+2 IF (A)=0 THEN (PC)←(PC)+relative offset Number of bytes :2 Number of cycles :2 Flags : C 0 AC F0 Byte 2 (PSW) Description : Control is shifted to a relative jump address if the accumulator contents are 0.
MSM80C154S/83C154S/85C154HVS Example JZ EMPTY LOC OBJ SOURCE 0099 04 EMPTY:INC A 00CA 60CD CHECK:JZ EMPTY 7 Instruction code 0 : 0 1 1 0 0 0 0 0 Byte 1 7 0 1 1 0 0 1 1 0 1 Byte 2 Before execution Accumulator After execution Accumulator 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 0 Program counter Program counter 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 15 0 8 7 0 308 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 15 8 7 0
DESCRIPTION OF INSTRUCTIONS 50.
MSM80C154S/83C154S/85C154HVS 51. LJMP code address (Long jump) 7 Instruction code : 0 0 0 0 0 0 0 1 7 A9 7 Jump address A7 A8 Byte 2 0 A6 A5 Operation : (PC0~15)←A0~15 Number of bytes :3 Number of cycles :2 Flags : C Byte 1 0 A15 A14 A13 A12 A11 A10 Jump address 0 AC F0 A4 A3 A2 A1 A0 RS1 RS0 OV F1 P Byte 3 (PSW) Description : Jump address A0~15 specified by operand are placed in the program counter PC0~15.
DESCRIPTION OF INSTRUCTIONS 52. MOV @Rr, #data (Move immediate data to indirect address) 7 Instruction code : 0 0 1 1 1 0 1 1 7 I7 Data address Byte 1 0 I6 I5 I4 I3 Operation : ((Rr))←#data r=0 or 1 Number of bytes :2 Number of cycles :1 Flags : C r AC F0 I2 RS1 RS0 OV I1 I0 F1 P Byte 2 (PSW) Description : An 8-bit immediate data value is copied to the data memory location addressed by the register r contents.
MSM80C154S/83C154S/85C154HVS 53. MOV @Rr, A (Move accumulator to indirect address) 7 1 0 Instruction code : Operation : ((Rr))←(A) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : C 1 AC 1 F0 1 0 1 RS1 RS0 OV 1 r F1 P Byte 1 (PSW) Description : The accumulator contents are copied to the data memory location addressed by the register r contents.
DESCRIPTION OF INSTRUCTIONS 54. MOV @Rr, data address (Move memory to indirect address) 7 Instruction code : 1 0 0 1 0 0 1 1 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 Operation : ((Rr))←(data address) r=0 or 1 Number of bytes :2 Number of cycles :2 Flags : C r AC F0 RS1 RS0 OV a1 a0 F1 P Byte 2 (PSW) Description : The specified data address contents are copied to the data memory location addressed by the register r contents.
MSM80C154S/83C154S/85C154HVS 55. MOV A, #data (Move immediate data to accumulator) 7 Instruction code : 0 0 1 1 1 0 1 0 7 I7 #data I6 : (A)←#data Number of bytes :2 Number of cycles :1 Flags : AC I5 F0 I4 I3 I2 RS1 RS0 OV (PSW) Description Byte 1 0 Operation C 0 I1 I0 F1 P Byte 2 • : An 8-bit immediate data is copied to the accumulator, and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 56. MOV A, @Rr (Move indirect address to accumulator) 7 0 Instruction code : Operation : (A)←((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : 1 C 1 AC 1 F0 0 0 1 RS1 RS0 OV 1 r F1 P (PSW) Description Byte 1 • : The data memory location contents addressed by the register r contents are copied to the accumulator, and the flag is updated.
MSM80C154S/83C154S/85C154HVS 57. MOV A, Rr (Move register to accumulator) 7 0 Instruction code : Operation : (A)←(Rr) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : 1 C 1 AC 1 F0 0 1 r2 RS1 RS0 OV r1 r0 F1 P (PSW) Description Byte 1 • : The register r contents are copied to the accumulator, and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 58. MOV A, data address (Move memory to accumulator) 7 Instruction code : 1 0 1 1 0 0 1 0 7 a7 Data address a6 a5 a4 a2 a1 a0 RS1 RS0 OV F1 P : (A)←(data address) Number of bytes :2 Number of cycles :1 Flags : AC F0 a3 (PSW) Description Byte 1 0 Operation C 1 Byte 2 • : The specified data address contents are copied to the accumulator, and the flag is updated.
MSM80C154S/83C154S/85C154HVS 59. MOV C, bit address (Move bit to carry flag) 7 Instruction code : 1 0 0 1 0 0 0 1 7 b7 Bit address b6 b5 b4 b2 b1 b0 RS1 RS0 OV F1 P : (C)←(bit address) Number of bytes :2 Number of cycles :1 Flags : (PSW) Description Byte 1 0 Operation C 0 AC F0 b3 Byte 2 • : The specified bit address content is copied to the carry flag. Example MOV C, P3.
DESCRIPTION OF INSTRUCTIONS 60. MOV DPTR, #data (Move immediate data to data pointer) 7 Instruction code 1 : 0 0 0 1 0 0 0 7 I15 #data I7 I14 I13 I12 I11 I10 I9 I6 I5 Number of bytes Number of cycles :2 Flags : C I8 Byte 2 0 : (DPTR)←#data (DPH)←I8~15 (DPL)←I0~7 :3 Operation Byte 1 0 7 #data 0 AC F0 I4 I3 I2 RS1 RS0 OV I1 I0 F1 P Byte 3 (PSW) Description : A 16-bit immediate data value is copied to the data pointer (DPH·DPL).
MSM80C154S/83C154S/85C154HVS 61. MOV Rr, #data (Move immediate data to register) 7 Instruction code : 0 0 1 1 1 1 r2 r1 7 I7 #data Byte 1 0 I6 I5 I4 I3 Operation : (Rr)←#data r=0 thru 7 Number of bytes :2 Number of cycles :1 Flags : C r0 AC F0 I2 RS1 RS0 OV I1 I0 F1 P Byte 2 (PSW) Description : An 8-bit immediate data value is copied to the register r.
DESCRIPTION OF INSTRUCTIONS 62. MOV Rr, A (Move accumulator to register) 7 0 Instruction code : Operation : (Rr)←(A) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : 1 C 1 AC 1 F0 1 1 r2 RS1 RS0 OV r1 r0 F1 P Byte 1 (PSW) Description : The accumulator contents are copied to the register r.
MSM80C154S/83C154S/85C154HVS 63. MOV Rr, data address (Move memory to register) 7 Instruction code : 1 0 0 1 0 1 r2 r1 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 Operation : (Rr)←(data address) r=0 thru 7 Number of bytes :2 Number of cycles :2 Flags : C r0 AC F0 RS1 RS0 OV a1 a0 F1 P Byte 2 (PSW) Description : The specified data address contents are copied to the register r.
DESCRIPTION OF INSTRUCTIONS 64. MOV bit address, C (Move carry flag to bit) 7 Instruction code : 1 0 0 0 1 0 0 1 7 b7 Bit address Byte 1 0 b6 b5 b4 b2 b1 b0 RS1 RS0 OV F1 P Operation : (bit address)←(C) Number of bytes :2 Number of cycles :2 Flags : C 0 AC F0 b3 Byte 2 (PSW) Description : The carry flag content is copied to the specified bit address. Example MOV P1.
MSM80C154S/83C154S/85C154HVS 65. MOV data address, #data (Move immediate data to memory) 7 Instruction code 0 : 0 1 1 1 0 1 0 7 a7 Data address I7 a6 a5 a4 a3 a2 a1 a0 Byte 2 0 I6 I5 I4 I3 Operation : (data address)←#data Number of bytes :3 Number of cycles :2 Flags : C Byte 1 0 7 #data 1 AC F0 I2 RS1 RS0 OV I1 I0 F1 P Byte 3 (PSW) Description : An 8-bit immediate data value is copied to the specified data address.
DESCRIPTION OF INSTRUCTIONS 66. MOV data address, @Rr (Move indirect address to memory) 7 Instruction code : 1 0 0 0 0 0 1 1 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 Operation : (data address)←((Rr)) r=0 or 1 Number of bytes :2 Number of cycles :2 Flags : C r AC F0 RS1 RS0 OV a1 a0 F1 P Byte 2 (PSW) Description : The data memory location contents addressed by the register r contents are copied to the specified data address.
MSM80C154S/83C154S/85C154HVS 67. MOV data address, A (Move accumulator to memory) 7 Instruction code : 1 0 1 1 1 0 1 0 7 a7 Data address Byte 1 0 a6 a5 a4 a2 a1 a0 RS1 RS0 OV F1 P Operation : (data address)←(A) Number of bytes :2 Number of cycles :1 Flags : C 1 AC F0 a3 Byte 2 (PSW) Description : The accumulator contents are copied to the specified data address.
DESCRIPTION OF INSTRUCTIONS 68. MOV data address, Rr (Move register to memory) 7 Instruction code : 1 0 0 0 0 1 r2 r1 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 Operation : (data address)←(Rr) r=0 thru 7 Number of bytes :2 Number of cycles :2 Flags : C r0 AC F0 RS1 RS0 OV a1 a0 F1 P Byte 2 (PSW) Description : The register r contents are copied to the specified data address.
MSM80C154S/83C154S/85C154HVS 69.
DESCRIPTION OF INSTRUCTIONS 70.
MSM80C154S/83C154S/85C154HVS 71.
DESCRIPTION OF INSTRUCTIONS 72. MOVX @DPTR, A (Move accumulator to external memory addressed by data pointer) 7 0 Instruction code : Operation : ((DPTR))←(A) Number of bytes :1 Number of cycles :2 Flags : 1 C 1 AC 1 F0 1 0 0 RS1 RS0 OV 0 0 F1 P Byte 1 (PSW) Description : The accumulator contents are stored in external data memory (RAM) addressed by the data pointer contents.
MSM80C154S/83C154S/85C154HVS 73. MOVX @Rr, A (Move accumulator to external memory addressed by register) 7 0 Instruction code : Operation : ((Rr))←(A) r=0 or 1 Number of bytes :1 Number of cycles :2 Flags : 1 C 1 AC 1 F0 1 0 0 RS1 RS0 OV 1 r F1 P Byte 1 (PSW) Description : The accumulator contents are stored in external data memory addressed by the register r contents.
DESCRIPTION OF INSTRUCTIONS 74. MOVX A, @DPTR (Move external memory addressed by data pointer to accumulator) 7 0 Instruction code : Operation : (A)←((DPTR)) Number of bytes :1 Number of cycles :2 Flags : 1 C 1 AC 1 F0 0 0 0 RS1 RS0 OV (PSW) 0 0 F1 P Byte 1 • Description : External data memory (RAM) contents addressed by the data pointer are stored in the accumulator, and the flag is updated.
MSM80C154S/83C154S/85C154HVS 75. MOVX A, @Rr (Move external memory addressed by register to accumulator) 7 0 Instruction code : Operation : (A)←((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :2 Flags : 1 C 1 AC 1 F0 0 0 0 RS1 RS0 OV 1 r F1 P (PSW) Description Byte 1 • : External data memory (RAM) contents addressed by the register r contents are stored in the accumulator, and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 76. MUL AB (Multiply accumulator by B) 7 1 0 0 1 Instruction code : Operations : (A)0~7←(A) × (B) (B)8~15 Number of bytes :1 Number of cycles :4 Flags : C F0 0 1 RS1 RS0 OV • (PSW) Description AC 0 0 0 F1 P • Byte 1 • : The accumulator contents are multiplied by the arithmetic operation register (B) contents. The operand is always handled as an integer without sign.
MSM80C154S/83C154S/85C154HVS 77. NOP (No operation) 7 0 Instruction code : Operation : (PC)←(PC)+1 Number of bytes :1 Number of cycles :1 Flags : 0 C 0 AC 0 F0 0 0 0 RS1 RS0 OV 0 0 F1 P Byte 1 (PSW) Description : The program counter is incremented by 1 without any other change in the CPU. Control is shifted to the next instruction.
DESCRIPTION OF INSTRUCTIONS 78. ORL A, #data (Logical OR immediate data to accumulator) 7 Instruction code : 0 0 1 0 0 0 1 0 7 I7 #data I6 I5 I4 : (A)←(A) OR #data Number of bytes :2 Number of cycles :1 Flags : AC F0 I3 I2 RS1 RS0 OV (PSW) Description Byte 1 0 Operation C 0 I1 I0 F1 P Byte 2 • : The logical OR between an 8-bit immediate data value and the accumulator contents is determined. The result is placed in the accumulator and the flag is updated.
MSM80C154S/83C154S/85C154HVS 79. ORL A, @Rr (Logical OR indirect address to accumulator) 7 0 0 Instruction code : Operation : (A)←(A) OR ((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : C 1 AC 0 F0 0 0 1 RS1 RS0 OV 1 r F1 P (PSW) Description Byte 1 • : The logical OR between the accumulator contents and the data memory location contents addressed by the register r contents is determined. The result is placed in the accumulator and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 80. ORL A, Rr (Logical OR register to accumulator) 7 0 Instruction code : Operation : (A)←(A) OR (Rr) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : 0 C 1 0 AC F0 0 1 r2 RS1 RS0 OV r1 r0 F1 P (PSW) Description Byte 1 • : The logical OR between the accumulator contents and the register r contents is determined. The result is placed in the accumulator and the flag is updated.
MSM80C154S/83C154S/85C154HVS 81. ORL A, data address (Logical OR memory to accumulator) 7 Instruction code : 0 0 1 0 0 0 1 0 7 a7 Data address a6 a5 a4 a3 a2 a1 a0 RS1 RS0 OV F1 P : (A)←(A) OR (data address) Number of bytes :2 Number of cycles :1 Flags : AC F0 (PSW) Description Byte 1 0 Operation C 1 Byte 2 • : The logical OR between the accumulator contents and the specified data address contents is determined.
DESCRIPTION OF INSTRUCTIONS 82. ORL C, bit address (Logical OR bit to carry flag) 7 Instruction code : 0 0 1 1 1 0 0 1 7 b7 Bit address b6 b5 b4 b3 b2 b1 b0 RS1 RS0 OV F1 P : (C)←(C) OR (bit address) Number of bytes :2 Number of cycles :2 Flags : (PSW) Description Byte 1 0 Operation C 0 AC F0 Byte 2 • : The logical OR between the carry flag and the specified bit address content is determined. The result is placed in the carry flag. Example ORL C, ACC.
MSM80C154S/83C154S/85C154HVS 83. ORL C,/bit address (Logical OR complement of bit to carry flag) 7 Instruction code : 0 1 0 1 0 0 0 0 7 b7 Bit address b6 b5 b4 b3 b2 b1 b0 RS1 RS0 OV F1 P : (C)←(C) OR (bit address) Number of bytes :2 Number of cycles :2 Flags : (PSW) Description Byte 1 0 Operation C 0 AC F0 Byte 2 • : The logical OR between the carry flag and the complement of specified bit address content is determined. The result is placed in the carry flag.
DESCRIPTION OF INSTRUCTIONS 84.
MSM80C154S/83C154S/85C154HVS 85. ORL data address, A (Logical OR accumulator to memory) 7 Instruction code : 0 0 1 0 0 0 0 1 7 a7 Data address Byte 1 0 a6 a5 a4 a3 a2 a1 Operation : (data address)←(data address) OR (A) Number of bytes :2 Number of cycles :1 Flags : C 0 AC F0 RS1 RS0 OV F1 a0 Byte 2 P (PSW) Description : The logical OR between the accumulator and the specified data address contents is determined. The result is placed in the specified data address.
DESCRIPTION OF INSTRUCTIONS 86. POP data address (Pop stack to memory) 7 Instruction code : 1 0 1 0 1 0 0 0 0 7 a7 Data address 0 a6 a5 a4 a2 a1 a0 RS1 RS0 OV F1 P Operations : (data address)←((SP)) (SP)←(SP)–1 Number of bytes :2 Number of cycles :2 Flags : C Byte 1 AC F0 a3 Byte 2 (PSW) Description : Stack contents addressed by the stack pointer are popped in the specified data address, and the stack pointer is decremented by 1. Example POP PSW:No change to parity bit.
MSM80C154S/83C154S/85C154HVS 87. PUSH data address (Push memory onto stack) 7 Instruction code : 1 0 1 0 0 0 0 0 0 7 a7 Data address 0 a6 a5 a4 a2 a1 a0 RS1 RS0 OV F1 P Operations : (SP)←(SP)+1 ((SP))←(data address) Number of bytes :2 Number of cycles :2 Flags : C Byte 1 AC F0 a3 Byte 2 (PSW) Description : The stack pointer is incremented by 1, and the specified data address contents are pushed in the stack addressed by the stack pointer.
DESCRIPTION OF INSTRUCTIONS 88. RET (Return from subroutine, non interrupt) 7 0 Instruction code : Operations : (PC8~15)←((SP)) (SP)←(SP)–1 (PC0~7)←((SP)) (SP)←(SP)–1 Number of bytes :1 Number of cycles :2 Flags : 0 C 0 AC 1 F0 0 0 0 RS1 RS0 OV 1 0 F1 P Byte 1 (PSW) Description : The stack contents addressed by the stack pointer are popped in the upper order 8 thru 15 of the program counter, and the stack pointer is decremented by 1.
MSM80C154S/83C154S/85C154HVS 89. RETI (Return from interrupt routine) 7 0 0 Instruction code : Operations : (PC8~15)←((SP)) (SP)←(SP)–1 (PC0~7)←((SP)) (SP)←(SP)–1 *INTERRUPT ENABLE Number of bytes :1 Number of cycles :2 Flags : C 0 AC 1 F0 1 0 0 RS1 RS0 OV 1 0 F1 P Byte 1 (PSW) Description : This return instruction functions as an interrupt routine terminating instruction.
DESCRIPTION OF INSTRUCTIONS 90. RL A (Rotate accumulator left) 7 Instruction code : Operation : 0 0 0 1 0 0 0 1 7 :1 Number of cycles :1 Flags : C Byte 1 Accumulator ← ← ← ← ← ← ← ← C Number of bytes 1 AC F0 0 RS1 RS0 OV F1 P (PSW) Description : All accumulator bits are shifted by one bit to the left. The MSB (bit 7) is shifted to the LSB bit position (bit 0).
MSM80C154S/83C154S/85C154HVS 91. RLC A (Rotate accumulator and carry flag left) 7 Instruction code : Operation : 0 0 0 Carry C 1 1 0 0 1 :1 Number of cycles :1 Flags : C (PSW) Description AC Byte 1 Accumulator ← ← ← ← ← ← ← ← 7 Number of bytes 1 F0 0 RS1 RS0 OV F1 • P • : The accumulator and the carry flag are connected, and all bits are shifted by one bit to the left.
DESCRIPTION OF INSTRUCTIONS 92. RR A (Rotate accumulator right) 7 Instruction code : Operation : 0 0 0 0 0 0 0 1 7 :1 Number of cycles :1 Flags : C Byte 1 Accumulator ← ← ← ← ← ← ← ← C Number of bytes 1 AC F0 0 RS1 RS0 OV F1 P (PSW) Description : All accumulator bits are shifted by one bit to the right. The LSB (bit 0) is shifted to the MSB bit position (bit 7).
MSM80C154S/83C154S/85C154HVS 93. RRC A (Rotate accumulator and carry flag right) 7 Instruction code : Operation : 0 0 0 Carry C 0 1 0 0 1 :1 Number of cycles :1 Flags : C (PSW) Description AC Byte 1 Accumulator ← ← ← ← ← ← ← ← 7 Number of bytes 1 F0 0 RS1 RS0 OV F1 • P • : The accumulator and the carry flag are connected, and all bits are shifted by one bit to the right.
DESCRIPTION OF INSTRUCTIONS 94. SETB C (Set carry flag) 7 Instruction code : 1 Operation : (C)←1 Number of bytes :1 Number of cycles :1 Flags : C (PSW) Description 0 1 0 AC F0 1 0 0 RS1 RS0 OV 1 1 F1 P • : The carry flag is cleared to 1.
MSM80C154S/83C154S/85C154HVS 95. SETB bit address (Set bit) 7 Instruction code : 1 0 1 0 1 0 0 1 7 b7 Bit address Byte 1 0 b6 b5 Operation : (bit address)←1 Number of bytes :2 Number of cycles :1 Flags : C 0 AC F0 b4 b3 b2 b1 b0 RS1 RS0 OV F1 P Byte 2 (PSW) Description : The specified bit address content is set to 1. Example SETB IE.
DESCRIPTION OF INSTRUCTIONS 96. SJMP code address (Short jump) 7 Instruction code : 1 0 0 0 0 0 0 0 7 R7 Relative offset Byte 1 0 R6 R5 R4 R3 R2 R1 R0 RS1 RS0 OV F1 P Operations : (PC)←(PC)+2 (PC)←(PC)+relative offset Number of bytes :2 Number of cycles :2 Flags : C 0 AC F0 Byte 2 (PSW) Description : Relative offset jump data is added/subtracted to/from the program counter contents following an increment.
MSM80C154S/83C154S/85C154HVS Example SJMP CHECK LOC OBJ SOURCE 0111 8010 SJUMP:SJMP CHECK 0123 33 CHECK:RLC A 7 Instruction code 0 : 1 0 0 0 0 0 0 0 Byte 1 7 0 0 0 0 1 0 0 0 0 Byte 2 Before execution After execution Program counter Program counter 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 15 8 7 0 356 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 15 8 7 0
DESCRIPTION OF INSTRUCTIONS 97. SUBB A, #data (Substract immediate data from accumulator with borrow) 7 Instruction code : 1 0 0 0 1 0 1 0 7 I7 #data I6 I5 I4 I3 : (A)←(A)–((C)+#data) Number of bytes :2 Number of cycles :1 Flags : Description Byte 1 0 Operation (PSW) 0 C AC • • F0 I2 RS1 RS0 OV I1 I0 F1 P • Byte 2 • : The carry flag content and an immediate data value are substracted from the accumulator contents.
MSM80C154S/83C154S/85C154HVS 98. SUBB A, @Rr (Substract indirect address from accumulator with borrow) 7 1 0 Instruction code : Operation : (A)←(A)–((C)+((Rr))) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : (PSW) Description 0 C AC • • 0 F0 1 0 1 RS1 RS0 OV 1 r F1 P • Byte 1 • : The carry flag content and the data memory location contents addressed by the register r contents are substracted from the accumulator contents.
DESCRIPTION OF INSTRUCTIONS 99. SUBB A, Rr (Substract register from accumulator with borrow) 7 0 Instruction code : Operation : (A)←(A)–((C)+(Rr)) Number of bytes :1 Number of cycles :1 Flags : 1 (PSW) Description 0 C AC • • 0 F0 1 1 r2 RS1 RS0 OV r1 r0 F1 P • Byte 1 • : The carry flag content and the register r contents are substracted from the accumulator contents. The result is placed in the accumulator, and the flags are updated.
MSM80C154S/83C154S/85C154HVS 100. SUBB A, data address (Substract memory from accumulator with borrow) 7 Instruction code : 1 0 0 0 1 0 1 0 0 7 a7 Data address 0 a6 a5 a4 a3 a2 a1 a0 RS1 RS0 OV F1 P Operation : (A)←(A)–((C)+(data address)) Number of bytes :2 Number of cycles :1 Flags : (PSW) Description Byte 1 C AC • • F0 • Byte 2 • : The carry flag contents and the specified data address contents are substracted from the accumulator contents.
DESCRIPTION OF INSTRUCTIONS 101.
MSM80C154S/83C154S/85C154HVS 102. XCH A, @Rr (Exchange indirect address with accumulator) 7 1 0 Instruction code : Operation : (A)→ ←((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : C 1 AC 0 F0 0 0 1 RS1 RS0 OV 1 r F1 P (PSW) Description Byte 1 • : The accumulator contents are exchanged with the data memory location contents addressed by the register r, and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 103. XCH A, Rr (Exchange register with accumulator) 7 1 0 Instruction code : Operation : (A)→ ←(Rr) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : C 1 0 AC F0 0 1 r2 RS1 RS0 OV r1 r0 F1 P (PSW) Description Byte 1 • : The accumulator contents are exchanged with the register r contents, and the flag is updated.
MSM80C154S/83C154S/85C154HVS 104. XCH A, data address (Exchange memory with accumulator) 7 Instruction code : 1 0 1 0 0 0 1 0 7 a7 Data address a6 a5 a4 a2 a1 a0 RS1 RS0 OV F1 P Operation Number of bytes :2 Number of cycles :1 Flags : AC F0 a3 (PSW) Description Byte 1 0 : (A)→ ←(data address) C 1 Byte 2 • : The accumulator contents are exchanged with the specified data address contents, and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 105. XCHD A, @Rr (Exchange low nibbles of indirect address with accumulator) 7 1 0 Instruction code : Operation : (A0~3)→ ←((Rr0~3)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : C 1 AC 0 F0 1 0 1 RS1 RS0 OV 1 r F1 P (PSW) Description Byte 1 • : The lower order bits (0 thru 3) of the accumulator contents are exchanged with contents of the lower order bits (0 thru 3) of the data memory location addressed by the register r contents.
MSM80C154S/83C154S/85C154HVS 106. XRL A, #data (Logical exclusive OR immediate data to accumulator) 7 Instruction code : 0 0 1 1 0 0 1 0 7 I7 #data I6 I5 I4 : (A)←(A) XOR #data Number of bytes :2 Number of cycles :1 Flags : AC F0 I3 I2 RS1 RS0 OV (PSW) Description Byte 1 0 Operation C 0 I1 I0 F1 P Byte 2 • : The exclusive OR operation is executed between an immediate data value and the accumulator contents.
DESCRIPTION OF INSTRUCTIONS 107. XRL A, @Rr (Logical exclusive OR indirect address to accumulator) 7 0 0 Instruction code : Operation : (A)←(A) XOR ((Rr)) r=0 or 1 Number of bytes :1 Number of cycles :1 Flags : C 1 AC 1 F0 0 0 1 RS1 RS0 OV 1 r F1 P (PSW) Description Byte 1 • : The exclusive OR operation is executed between the accumulator contents and the data memory location contents addressed by the register r contents.
MSM80C154S/83C154S/85C154HVS 108. XRL A, Rr (Logical exclusive OR register to accumulator) 7 0 0 Instruction code : Operation : (A)←(A) XOR (Rr) r=0 thru 7 Number of bytes :1 Number of cycles :1 Flags : C 1 1 AC F0 0 1 r2 RS1 RS0 OV r1 r0 F1 P (PSW) Description Byte 1 • : The exclusive OR between the accumulator contents and the register r contents is determined. The result is stored in the accumulator and the flag is updated.
DESCRIPTION OF INSTRUCTIONS 109. XRL A, data address (Logical exclusive OR memory to accumulator) 7 Instruction code : 0 0 1 1 0 0 1 0 7 a7 Data address a6 a5 a4 a3 a2 a1 a0 RS1 RS0 OV F1 P : (A)←(A) XOR (data address) Number of bytes :2 Number of cycles :1 Flags : AC F0 (PSW) Description Byte 1 0 Operation C 1 Byte 2 • : The exclusive OR between the accumulator contents and the specified data address contents is determined.
MSM80C154S/83C154S/85C154HVS 110.
DESCRIPTION OF INSTRUCTIONS 111. XRL data address, A (Logical exclusive OR accumulator to memory) 7 Instruction code : 0 0 1 1 0 0 0 1 7 a7 Data address a6 a5 a4 a3 a2 a1 : (data address)←(data address) XOR (A) Number of bytes :2 Number of cycles :1 Flags : AC F0 RS1 RS0 OV (PSW) Description Byte 1 0 Operation C 0 F1 a0 Byte 2 P • : The exclusive OR between the accumulator and the specified data address contents is determined.
