User's Manual

MSM80C154S/83C154S/85C154HVS
258
13. ANL A, Rr (Logical AND register to accumulator)
01011r2 r1 r0
70
Instruction code
Operation
Number of bytes
Number of cycles
Flags
(PSW)
Description
Example ANL A, R5
Instruction code
: Byte 1
(A)←(A) AND (Rr) r=0 thru 7:
C AC F0 RS1 RS0 OV F1 P
•
:
:
:
The logical AND between the accumulator contents and the
register r contents is determined. The result is placed in the
accumulator and the flag is updated.
:
01011101
70
Byte 1
Accumulator
11011011
70
1
1
Before execution
Accumulator
01010001
70
After execution
:
Register 5
01010101
70
Register 5
01010101
70