Modem User Manual

LZT 123 1834 48
VREF exceeds it’s reset threshold approx 500µs later, then 250ms afterwards
(denoted by t
2
) the RESET line goes high. The microprocessor can latch the power on
state by setting the power keep
(PWR_KEEP) high after the RESET goes high and
before the power on (ON/OFF) signal is released.
It is recommended that ON/OFF is held low for at least 450ms to guarantee
completion of the power up sequence.
5.8.2 Turning the Module Off
VCC
ON/OFF
VREF
(RESET)
(PWR_KEEP)
reset threshold
t
3
P_ON
pulled low
Power down
sequence complete
power
removed
Figure 5.8-2 Power Down timing
Powering the GR64 power down sequence is shown above. The significant signals
are VCC, ON/OFF and VREF, shown by solid lines. The other signals (in dashed lines)
are internal to the module and are shown for reference purposes only.
With the module powered normally, ON/OFF is pulled-up to VCC potential. In order
to power down the module, ON/OFF is pulled to ground. Once ON/OFF has been
held low for at least 125ms the shut-down procedure begins. Although ON/OFF can
be held low for longer, it will delay completion of the shut-down event. If the
module is registered on a GSM network, the de-registration process will complete;
this may last between 3 to 30 seconds. The power latch (PWR_KEEP) is released and
approximately 70ms later the LDO outputs fall.
For module variants where VREF is an output, the absence of VREF is a useful
indicator that the network de-registration and shut-down is complete. Once VREF is
no longer present, the application can safely remove VCC.