AR-B1474 INDUSTRIAL GRADE 486DX/DX2/DX4 CPU CARD User’ s Guide Edition: 3.1 Book Number: AR-B1474-99.
AR-B1474 User¡¦s Guide Table of Contents 0. PREFACE....................................................................................................................................................... 0-3 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1. OVERVIEW..................................................................................................................................................... 1-1 1.1 1.2 1.3 2. COPYRIGHT NOTICE AND DISCLAIMER ...........................................................
AR-B1474 User¡¦s Guide 5.4 ROM DISK INSTALLATION ........................................................................................................................................................5-6 5.4.1 UV EPROM (27Cxxx)..........................................................................................................................................................5-6 5.4.2 Large Page 5V FLASH Disk................................................................................................
AR-B1474 User¡¦s Guide 0.PREFACE 0.1 COPYRIGHT NOTICE AND DISCLAIMER September 1995 Acrosser Technology makes no representations or warranties with respect to the contents hereof and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
AR-B1474 User¡¦s Guide 0.6 ORGANIZATION This information for users covers the following topics (see the Table of Contents for a detailed listing): l l l l l l l l l l Chapter 1, “Overview”, provides an overview of the system features and packing list. Chapter 2, “System Controller” describes the major structure. Chapter 3, “Setting Up the System”, describes how to adjust the jumper, and the connectors setting.
AR-B1474 User¡¦s Guide 1. OVERVIEW This chapter provides an overview of your system features and capabilities. The following topics are covered: l l l Introduction Packing List Features 1.1 INTRODUCTION The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation in harsh environments. The total on-board memory for the AR-B1474 can be configured from 1MB to 32MB by using all 72-pin type DRAM devices.
AR-B1474 User¡¦s Guide 1.2 PACKING LIST The accessories are included with the system. Before you begin installing your AR-B1474 card, take a moment to make sure that the following items have been included inside the AR-B1474 package.
AR-B1474 User¡¦s Guide 2. SYSTEM CONTROLLER This chapter describes the major structure of the AR-B1474 serial CPU board. The following topics are covered: l l l l l DMA Controller Keyboard Controller Interrupt Controller Serial Port Parallel Port 2.1 DMA CONTROLLER The equivalent of two 8237A DMA controllers are implemented in the AR-B1474 card.
AR-B1474 User¡¦s Guide 2.3 INTERRUPT CONTROLLER The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1474 card. They accept requests from peripherals, resolve priorities on pending interrupts in service, issue interrupt requests to the CPU, and provide vectors which are used as acceptance indices by the CPU to determine which interrupt service routine to execute.
AR-B1474 User¡¦s Guide 2.3.
AR-B1474 User¡¦s Guide 2.3.2 Real-Time Clock and Non-Volatile RAM The AR-B1474 contains a real-time clock compartment that maintains the date and time in addition to storing configuration information about the computer system. It contains 14 bytes of clock and control registers and 114 bytes of general purpose RAM. Because of the use of CMOS technology, it consumes very little power and can be maintained for long period of time using an internal Lithium battery.
AR-B1474 User¡¦s Guide 2.3.
AR-B1474 User¡¦s Guide 2.3.5 ISA Bus Signal Description Name Description BUSCLK [Output] The BUSCLK signal of the I/O channel is asynchronous to the CPU clock. RSTDRV [Output] This signal goes high during power-up, low line-voltage or hardware reset SA0 - SA19 The System Address lines run from bit 0 to 19.
AR-B1474 User¡¦s Guide Name Description -MASTER [Input] The MASTER is the signal from the I/O processor which gains control as the master and should be held low for a maximum of 15 microseconds or system memory may be lost due to the lack of refresh -MEMCS16 [Input, The Memory Chip Select 16 indicates that the present Open data transfer is a 1-wait state, 16-bit data memory collector] operation -IOCS16 [Input, The I/O Chip Select 16 indicates that the present data Open transfer is a 1-wait state, 1
AR-B1474 User¡¦s Guide (3) Interrupt Enable Register (IER) Bit 0: Enable Received Data Available Interrupt (ERBFI) Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI) Bit 2: Enable Receiver Line Status Interrupt (ELSI) Bit 3: Enable MODEM Status Interrupt (EDSSI) Bit 4: Must be 0 Bit 5: Must be 0 Bit 6: Must be 0 Bit 7: Must be 0 (4) Interrupt Identification Register (IIR) Bit 0: “0” if Interrupt Pending Bit 1: Interrupt ID Bit 0 Bit 2: Interrupt ID Bit 1 Bit 3: Must be 0 Bit 4: Must be 0 Bit 5: Must
AR-B1474 User¡¦s Guide (8) MODEM Status Register (MSR) Bit 0: Delta Clear to Send (DCTS) Bit 1: Delta Data Set Ready (DDSR) Bit 2: Training Edge Ring Indicator (TERI) Bit 3: Delta Receive Line Signal Detect (DSLSD) Bit 4: Clear to Send (CTS) Bit 5: Data Set Ready (DSR) Bit 6: Ring Indicator (RI) Bit 7: Received Line Signal Detect (RSLD) (9) Divisor Latch (LS, MS) LS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0: Bit 1: Bit 2: Bit 3: Bit 4: Bit 5: Bit 6: Bit 7: MS Bit 8 Bit 9 Bit 10 Bit 11 Bit 12
AR-B1474 User¡¦s Guide (3) Data Swapper The system microprocessor can read the contents of the printer’ s Data Latch through the Data Swapper by reading the Data Swapper address. (4) Printer Status Buffer The system microprocessor can read the printer status by reading the address of the Printer Status Buffer. The bit definitions are described as follows: 7 6 5 4 3 2 1 0 X X X -ERROR SLCT PE -ACK -BUSY Figure 2-2 Printer Status Buffer NOTE: X presents not used.
AR-B1474 User¡¦s Guide 3. SETTING UP THE SYSTEM This section describes pin assignments for system’ s external connectors and the jumpers setting. l l Overview System Setting 3.1 OVERVIEW The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation in harsh environments. The total on-board memory for the AR-B1474 can be configured from 1MB to 32MB by using all 72-pin type DRAM devices.
AR-B1474 User¡¦s Guide 3.2 SYSTEM SETTING Jumper pins allow you to set specific system parameters. Set them by changing the pin location of jumper blocks. (A jumper block is a small plastic-encased conductor that slips over the pins.) To change a jumper setting, remove the jumper from its current location with your fingers or small needle-nosed pliers. Place the jumper over the two pins designated for the desired setting. Press the jumper evenly onto the pins. Be careful not to bend the pins.
AR-B1474 User¡¦s Guide 3.2.2 Hard Disk (IDE) Connector (CN1) A 40-pin header type connector (CN1) is provided to interface with up to two embedded hard disk drives (IDE AT bus). This interface, through a 40-pin cable, allows the user to connect up to two drives in a “daisy chain” fashion. To enable or disable the hard disk controller, please use BIOS Setup program to select. The following table illustrates the pin assignments of the hard disk drive’ s 40-pin connector.
AR-B1474 User¡¦s Guide 3.2.4 FDD Port Connector (CN2) The AR-B1474 provides a 34-pin header type connector for supporting up to two floppy disk drives. To enable or disable the floppy disk controller, please use BIOS Setup program to select.
AR-B1474 User¡¦s Guide 3.2.
AR-B1474 User¡¦s Guide (3) PC/104 ISA Bus Signal Description Name Description BUSCLK [Output] The BUSCLK signal of the I/O channel is asynchronous to the CPU clock. RSTDRV [Output] This signal goes high during power-up, low line-voltage or hardware reset SA0 - SA19 The System Address lines run from bit 0 to 19.
AR-B1474 User¡¦s Guide Name Description -MASTER [Input] The MASTER is the signal from the I/O processor which gains control as the master and should be held low for a maximum of 15 microseconds or system memory may be lost due to the lack of refresh -MEMCS16 The Memory Chip Select 16 indicates that the present [Input, Open collector] data transfer is a 1-wait state, 16-bit data memory operation -IOCS16 The I/O Chip Select 16 indicates that the present data [Input, Open collector] transfer is a 1-wai
AR-B1474 User¡¦s Guide (4) CPU Clock Select (JP6 & JP9) For different type of CPUs, the clock generator and clock divisor need to be set by JP6 and JP9. The clock base is selected by JP6, JP9 is used to select single or half clock system. We recommend that you refer the following table for setting the CPU clock.
AR-B1474 User¡¦s Guide 3.2.8 Memory Setting (1) Cache RAM Size Select (JP8) The AR-B1474 can be configured to provide a write-back or write-through cache scheme and support 128KB to 512KB cache systems. A write-back cache system may provide better performance than a write-through cache system. The BIOS Setup program allows you to set the cache scheme either write-back or write-through, either the internal cache selection. The AR-B1474 needs four 32Kx8 SRAM chips to construct 128KB cache.
AR-B1474 User¡¦s Guide 3.2.9 LED Header (J1, J2 & J4) (1) External Power LED & Keyboard Lock Header (J4) 1 2 3 4 5 Power LED+ Not Used Power LEDKey-Lock+ Key-Lock- Figure 3-16 J4: Power LED & Key Lock Header (2) HDD LED Header (J1) 1 LED+ 2 LEDFigure 3-17 J1: HDD LED Header (3) Watchdog LED Header (J2) 1 LED+ 2 LEDFigure 3-18 J2: Watchdog LED Header 3.2.10 Keyboard Connector (1) 6-Pin Mini DIN Keyboard Connector (CN5) CN5 is a 6-pin Mini-DIN connector.
AR-B1474 User¡¦s Guide 3.2.11 External Speaker Header (J3) Besides the on board buzzer, you can use an external speaker by connecting J3 header directly. J3 1 2 3 4 Speaker+ SpeakerSpeakerSpeaker- Figure 3-21 J3: External Speaker Header 3.2.12 Reset Header (J7) J7 is used to connect to an external reset switch. Shorting these two pins will reset the system. 1 Reset+ 2 Reset1 2 Figure 3-22 J7: Reset Header 3.2.
AR-B1474 User¡¦s Guide 4. INSTALLATION This chapter describes the procedure of the installation. The following topics are covered: l l l l Overview Utility Diskette Write Protect Function Watchdog Timer 4.1 OVERVIEW This chapter provides information for you to set up a working system based on the AR-B1474 CPU card. Please read the details of the CPU card’ s hardware descriptions before installation carefully, especially jumpers setting, switch setting and cable connection.
AR-B1474 User¡¦s Guide 4.2 UTILITY DISKETTE To support the AR-B1474 solid state disk’ s operations, the following programs or files has been provided on the accompanying utility diskette: (1) PGM1474.EXE PGM1474.EXE PGM1474.EXE is used to program the 12V FLASH EPROM after the ROM pattern files are generated by RFG.EXE The PGM1474.EXE can also program the correctness of the ROM pattern files onto 5V FLASH EPROM (start from MEM1) or SRAM for testing the ROM pattern files. To execute PGM1474.
AR-B1474 User¡¦s Guide (2) WD1474.EXE WD1474.EXE This program demonstrates how to enable and trigger the watchdog timer. It allows you to test the function when the watchdog timer is enabled. (3) WP1474.EXE WP1474.EXE This program demonstrates how to enable and disable software write protected function. It also shows the current protect mode of write or read only memory. (4) BU1474.EXE BU1474.EXE BU1474.
AR-B1474 User¡¦s Guide stated in your PGF). The ROM pattern files will have the same file names, but will have different extension names. For example: TEST.R01, TEST.R02, TEST.R03 …etc. Display Error in PGF File This option displays errors that were detected in your PGF. Help to PGF File This option gives information on how to write a PGF file and how to generate ROM pattern files. An example PGF is also included. Move the reverse video bar to then press [ENTER].
AR-B1474 User¡¦s Guide 4.3 WRITE PROTECT FUNCTION The AR-B1474 provides hardware and software write protect functions for small page 5V FLASH disk and only software write protected function for SRAM disk. This is to prevent your data on 5V FLASH or SRAM disk from accidental deletion or overwrite. If your FLASH/SRAM disk is write protected, any write operation to the protected FLASH/SRAM disk will get a write protect error: Write protect error writing drive A About, Retry, Fail? 4.3.
AR-B1474 User¡¦s Guide 4.4 WATCHDOG TIMER This section describes how to use the Watchdog Timer, disabled, enabled, and trigger. The AR-B1474 is equipped with a programmable time-out period watchdog timer. This watchdog timer can be enabled by your program. Once you have enabled the watchdog timer, the program should trigger it every time before it times out.
AR-B1474 User¡¦s Guide If you want to generate IRQ15 signal to warn your program when watchdog times out, the following table listed the relation of timer factors between time-out period. Time Factor 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H Table 4-2 Time-Out Setting Time-Out Period (Seconds) 3 6 12 18 24 30 36 42 NOTE: 1.
AR-B1474 User¡¦s Guide 5.SOLID STATE DISK The section describes the various type SSDs’ installation steps as follows. This chapter describes the procedure of the installation. The following topics are covered: l l l l Overview Switch Setting Jumper Setting ROM Disk Installation 5.1 OVERVIEW The AR-B1474 provides three 32-pin JEDEC DIP sockets which may be populated with up to 3MB of EPROM or 1.5MB of FLASH or 1.5MB of SRAM disk.
AR-B1474 User¡¦s Guide 5.2.1 Overview There is 1 DIP Switch located on the AR-B1474. It performs the following functions: ON OFF 1 2 3 4 5 6 7 8 Figure 5-2 SW1: Switch Select SW1-1 & SW1-2 Set the base I/O port address SW1-3 & SW1-4 Set the starting memory address SW1-5 & SW1-6 Set the drive number of solid state disk SW1-7 & SW1-8 Set the used ROM memory chips 5.2.
AR-B1474 User¡¦s Guide 5.2.4 SSD Drive Number (SW1-5 & SW1-6) The AR-B1474 SSD can simulate one or two disk drives. You can assign the drive letter of the AR-B1474 by configuring SW1-5 & SW1-6. You can make the computer to boot from SSD by copying DOS into the SSD. If your SSD does not have DOS, the computer will boot from your hard disk or floppy disk. In this condition, the SSD BIOS of AR-B1474 will set the drive letter of the SSD to the desired drive letter automatically.
AR-B1474 User¡¦s Guide (2) Disk Drive Name Arrangement If any logical hard disk drives exist in your system, there will also be a different disk number depending on which version DOS you are using. The solid state disk drive number with there respective DOS drive designation are listed in table as follows. The solid state disk drive number is changeable as the DOS version. The following table expresses the variety. Floppy disk No.
AR-B1474 User¡¦s Guide 5.3 JUMPER SETTING Before installing the memory into memory sockets MEM1 through MEM3, you have to configure the memory type which will be used (ROM/RAM) on the AR-B1474. Each socket is equipped with a jumper to select the memory type. You can configure the AR-B1474 as a (FLASH) EPROM disk (ROM only), a SRAM disk (SRAM only) or a combination of (FLASH) EPROM and SRAM disk. It is not necessary to insert memory chips into all of the sockets.
AR-B1474 User¡¦s Guide 5.3.2 SSD Memory Type Setting (M1 ~ M3 & JP5) A B C JP5 1 2 1 2 3 3 M1, M2 & M3 A B C 1 1MX8 EPROM (Only) JP5 2 1 2 3 3 M1, M2 & M3 A B EPROM (128KX8, 256KX8 and 512KX8) 5V FLASH (64KX8, 128KX8 and 256KX8) (Factory Preset) C JP5 1 2 1 2 3 3 M1, M2 & M3 A B 5V FLASH (512KX8 Only) C JP5 1 2 1 2 3 3 M1, M2 & M3 SRAM Figure 5-4 M1~M3 & JP5: Memory Type Setting 5.4 ROM DISK INSTALLATION The section describes the various type SSDs’ installation steps as follows.
AR-B1474 User¡¦s Guide ON OFF 1 2 3 4 5 6 7 8 Figure 5-5 UV EPROM (27CXXX) Switch Setting A B C JP5 1 2 3 M1, M2 & M3 A B 1 2 3 1MX8 EPROM (Only) C JP5 1 2 1 2 3 3 M1, M2 & M3 EPROM (128KX8, 256KX8 and 512KX8) Figure 5-6 UV EPROM Jumper Setting (2) Software Programming Use the UV EPROM, please refer to the follow steps: Step 1: Turn on the power and boot DOS from hard disk drive or floppy disk drive. Step 2: Making a Program Group File (*.PGF file) Step 3: Using the RFG.
AR-B1474 User¡¦s Guide 5.4.2 Large Page 5V FLASH Disk If you are using large page 5V FLASH as ROM disk, it is the same procedure as step 1 to step 4 of using the UV EPROM. (2) Switch and Jumper Setting Step 1: Use jumper block to set the memory type as ROM (FLASH). Step 2: Select the proper I/O base port, firmware address, disk drive number and large page 5V FLASH type on SW1. Step 3: Insert programmed EPROM(s) or FLASH(s) chips into sockets starting at MEM1.
AR-B1474 User¡¦s Guide Step 4: Turn on your system, and Program FLASH EPROMs. NOTE: The FLASH EPROM program is built-in the AR-B1474 board. The FLASH EPROMs can be programmed on the AR-B1474. Before programming the FLASH EPROMs, please insert at least the same number of FLASH EPROMs, please insert at least the same number of FLASH EPROMs, please insert at least the same number of FLASH chips as the ROM pattern files generated. Step 5: The PGM1474.
AR-B1474 User¡¦s Guide A B C 1 JP5 2 1 2 3 3 (Factory Preset) M1, M2 & M3 5V/12V FLASH (64KX8, 128KX8 and 256KX8) A B C 1 JP5 2 3 1 2 3 5V FLASH (512KX8 Only) M1, M2 & M3 Figure 5-10 5V FLASH (29CXXX & 28EEXXX) Jumper Setting (2) Using Tool Program If small page 5V FLASH EPROMs are used, you can use the same method as step 1 to step 4 of using the UV EPROM: Step 1: Making a Program Group File (*.
AR-B1474 User¡¦s Guide CAUTION: It is not recommended that the user formatted the disk and copy files to the FLASH disk very often. Since the FLASH EPROM’ s write cycle life time is about 10,000 or 100,000 times, writing data to the FLASH too often will reduce the life time of the FLASH EPROM chips, especially the FLASH EPROM chip in the MEM1 socket. 5.4.4 RAM Disk (1) Jumper Setting Step 1: Use jumper block to set the memory type as ROM (FLASH).
AR-B1474 User¡¦s Guide 5.4.5 Combination of ROM and RAM Disk The AR-B1474 can be configured as a combination of one ROM disk and one RAM disk. Each disk occupies a drive unit. Step 1: Use jumper block to select the proper ROM/RAM configuration you are going to use. Step 2: Insert the first programmed EPROM into the socket mem1, the second into the socket MEM2, etc. Step 3: Insert the SRAM chips starting from the first socket assigned as SRAM.
AR-B1474 User¡¦s Guide (3) D.O.C. Setting (SW1-8) ON OFF 1 2 3 4 5 6 7 8 Figure 5-14 SW1-8: D.O.C. Setting Note: There is 1 DIP switch located on the AR-B1474. It performs the followings: SW1-1 & SW1-2 SW1-3 & SW1-4 SW1-5, SW1-6 & SW1-7 SW1-8 Set the base I/O port address Set the starting memory address The function now is unavailable Set the DiskOnChip only 5.5.2 Software Setting We will attach the BU1474.EXE and 1474DOC.INI these two files, BU1474.EXE is the utility program, and the 1474DOC.
AR-B1474 User¡¦s Guide 6. BIOS CONSOLE This chapter describes the AR-B1474 BIOS menu displays and explains how to perform common tasks needed to get up and running, and presents detailed explanations of the elements found in each of the BIOS menus. The following topics are covered: l l l l l l l l l l BIOS Setup Overview Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Power Management Auto-Detect Hard Disks Password Setting Load Default Setting BIOS Exit BIOS Update 6.
AR-B1474 User¡¦s Guide 6.2 STANDARD CMOS SETUP The option allows you to record some basic system hardware configuration and set the system clock and error handling. If the CPU board is already installed in a working system, you will not need to select this option anymore. Date & Time Setup Highlight the field and then press the [Page Up] /[Page Down] or [+]/[-] keys to set the current date. Follow the month, day and year format.
AR-B1474 User¡¦s Guide 6.3 ADVANCED CMOS SETUP The option consists of configuration entries that allow you to improve your system performance, or let you set up some system features according to your preference. System BootUp Sequence The option determines where the system looks first for an operating system. System BootUp Num-Lock This item is used to activate the Num Lock function upon system boot.
AR-B1474 User¡¦s Guide Internal Cache Memory This option specifies the caching algorithm used for L1 internal cache memory. The settings are: Setting Disabled WriteBack Description Neither L1 internal cache memory on the CPU or L2 secondary cache memory is enabled. Use the write-back caching algorithm. WriteThru Use the write-through caching algorithm. Table 6-1 Internal Cache Setting External Cache Memory This option specifies the caching algorithm used for L2 secondary (external) cache memory.
AR-B1474 User¡¦s Guide OnBoard FDC This option enables the floppy drive controller on the AR-B1474. OnBoard IDE This option Enabled/Disabled the use of the IDE controller on the AR-B1474. Parallel Port Address This option is used to select the port address and the IRQ of the on-board parallel port. The addresses are 378H, 278H, 3BCH, and Disable. The IRQs are IRQ5 & IRQ7 for selecting. Parallel Port Mode This option is specifies the parallel port mode. The settings are Printer or Extended (Bi-direction).
AR-B1474 User¡¦s Guide Parity Check This option enables or disables parity error checking for all system RAM. This option must be Disabled if the used DRAM SIMMs are 32-bit but not 36-bit devices. Slow Refresh This options sets the DRAM refresh cycle time. The settings are 15us, 30us, 60us, and 120us. Hidden Refresh Hidden refresh separates refreshing of AT-bus memory and local DRAM.
AR-B1474 User¡¦s Guide 6.6 AUTO-DETECT HARD DISKS This option detects the parameters of an IDE hard disk drive, and automatically enters them into the Standard CMOS Setup screen. 6.7 PASSWORD SETTING This BIOS Setup has an optional password feature. The system can be configured so that all users must enter a password every time the system boots or when BIOS Setup is executed. User can set either a Supervisor password or a User password. 6.7.
AR-B1474 User¡¦s Guide 6.9 BIOS EXIT This section is used to exit the BIOS main menu in two types situation. After making your changes, you can either save them or exit the BIOS menu and without saving the new values. 6.9.1 Save Settings and Exit This item set in the , , and the new password (if it has been changed) will be stored in the CMOS. The CMOS checksum is calculated and written into the CMOS.
AR-B1474 User¡¦s Guide 7. SPECIFICATIONS CPU: 25-100 MHz INTEL/AMD/CYRIX 80486DX/DX2/DX4 Bus Interface: ISA (PC-AT) Bus and PC/104 Bus Chipset: ALI M1429 and M1431 RAM Memory: 1MB to 32MB using 32-bit or 36-bit 72-pin SIMMs with access time of 70ns or less Shadow RAM: Up to 256KB in 32 KB blocks supports system and video BIOS Extended Memory Fully supports the LIM EMS 4.0 and 3.
AR-B1474 User¡¦s Guide 8. PLACEMENT & DIMENSIONS 8.
AR-B1474 User¡¦s Guide 8.2 DIMENSIONS 7290 540 150 3290 2900 294 4800 9−∅138 6300 540 765 3150 200 200 200 1700 3000 1900 3200 100 525 620 85 Unit: mil (1 inch = 25.
AR-B1474 User¡¦s Guide 9.MEMORY BANKS & PROGRAMMING RS-485 9.1 USING MEMORY BANK This section provides the information about how to access the memory on the AR-B1474 without using the ARB1474 SSD BIOS. The AR-B1474 hardware divides every 8K bytes of memory into a memory bank. To access the data in the memory, you have to assign the chip number and the bank number. On every chip, the memory bank number starts from zero. The last memory bank number depends on the size of the memory chip used on the ARB1474.
AR-B1474 User¡¦s Guide Example 1: Select the 10th bank of the MEM1 on the AR-B1474. The AR-B1474 is using 27C020 (256K*8), and the base port is &H210. 100 base_port=&H210 110 OUT base_port+0,&H59 Example 2: Select the 40th bank of MEM3 on the AR-B1474. The AR-B1474 is using 27C040 (512K*8), and the base port is &H390. 200 base_port=&H390 210 OUT base_port+0,&HD7 9.2 PROGRAMMING RS-485 The majority communicative operation of the RS-485 is in the same of the RS-232.
AR-B1474 User¡¦s Guide (3) Send out one block data (Transmit – the data more than two characters) Step 1: Enable TXC signal, and the bit 0 of the address of offset+4 just sets “1”. Step 2: Send out the data. (Write all data to the offset+0 of the current COM port address) Step 3: Wait for the buffer’ s data empty. Check transmitter holding register (THRE, bit 5 of the address of offset+5), and transmitter shift register (TSRE, bit 6 of the address of offset+5) are all sets must be “0”.
AR-B1474 User¡¦s Guide 10.SSD TYPES SUPPORTED & INDEX 10.
AR-B1474 User¡¦s Guide SGS-THOMSON TI TOSHIBA M27C2001 TMS27C020 TCS712000 (256Kx8, 2M bits) (256Kx8, 2M bits) (256Kx8, 2M bits) AMD ATMEL FUJITSU HITACHI INTEL MITSUBISHI NEC NS SGS-THOMSON TI TOSHIBA Am27C040 AT27C040 MBM27C4001 HN27C401 D27C040 M5M27C401 D27C4001 NM27C040 M27C4001 TMS27C040 TCS714000 (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) (512Kx8, 4M bits) ATM
AR-B1474 User¡¦s Guide 10.
