User Manual

Chapter 2: Installation
2-27
Power Button
OH/Fan Fail LED
1
NIC1 LED
Reset Button
2
HDD LED
Power LED
Reset
PWR
Vcc
Vcc
Vcc
Vcc
Ground
Ground
1920
Vcc
X
Ground
NMI
X
Vcc
PWR Fail LED
NIC2 LED
Power Button
The Power Button connection is located
on pins 1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be con-
gured to function as a suspend button
(with a setting in the BIOS - See Chapter
4). To turn off the power when the system
is in suspend mode, press the button for
4 seconds or longer. Refer to the table on
the right for pin denitions.
Power Button
Pin Denitions (JF1)
Pin# Denition
1 Signal
2 Ground
Reset Button
The Reset Button connection is located
on pins 3 and 4 of JF1. Attach it to a
hardware reset switch on the computer
case. Refer to the table on the right for
pin denitions.
Reset Button
Pin Denitions (JF1)
Pin# Denition
3 Reset
4 Ground
A. Reset Button
B. PWR Button
A
B
JPWR1
JPI2C1
LE1
JTPM1
FAN5
FAN7
FAN6
FAN3
FANA
J18
JSD1
SP1
BT1
J29
JBR1
JWD1
STBY1
JPI1
JL1
P2 DIMMH2
P2 DIMMG2
P2 DIMMH1
P2 DIMMG1
P2 DIMME2
P2 DIMMF1
P2 DIMMF2
P1 DIMMA2
P1 DIMMA1
P1 DIMMB2
P1 DIMMB1
P1 DIMMD2
P1 DIMMD1
P1 DIMMC1
USB4
CPU2 Slot5 PCI-E 3.0 x16
CPU1 Slot3 PCI-E 3.0 x16
CPU1 Slot2 PCI-E 3.0 x4 in x8
CPU1 Slot1 PCI-E 3.0 x16
TPM/Port80
USB5/6
JF1
Always Populate DIMMxA First
I-SATA5
I-SATA4
I-SATA3
I-SATA2
I-SATA1
COM1
USB3.0
0/1
I-SATA0
P1 DIMMC2
JPME1
FAN1
CPU2
JSPDIF_In
T-SGPIO1
JBT1
BIOS
JD1
LAN1/2
USB2.0
0/1/2/3
JPWR2
J22
Intel
C602
CPU2 Slot6 PCI-E 3.0 x8
J21
T-SGPIO2
KB/MS
7.1 Audio
Audio
CTRL
GLAN
CTRL
CPLD
S I/O
JPL1
JPL2
CPU2 Slot4 PCI-E 3.0 x8
CLK Buffer
Battery
PS2
USB3.0 2/3
USB 3.0 CTRL
FAN4
FP Audio Header
1394a
CTRL
(CPU1Fan)
(CPU2 Fan)
CNF1
JSPDIF_Out
CNF2
J30
JI2C2
JI2C1
JI2C2
JOH1
X9DAi
Rev.
1.02
I-SAS/
SATA0~3
CPU1
P2 DIMME1