User's Manual
Table Of Contents
- 1 Introduction
- 2 Block Diagram
- 3 Application Interface
- 3.1 Power Supply
- 3.2 Power-up / -down Slew-Rate
- 3.3 Reset
- 3.4 Supply Voltage Monitor
- 3.5 Serial Interface
- 3.6 GPIO Interface
- 3.7 I2C Interface0F
- 3.8 SPI Serial Peripheral Interface1F
- 1.1
- 3.9 Bluetooth Radio Interface
- 3.10 WLAN Coexistence Interface2F
- 3.11 Slow Clock Interface
- 3.12 Test Mode Enable
- 3.13 Pin Strapped System Memory Boot Mode Invocation
- 3.14 Operating in a Power-Switched Environment
- 3.15 Serial Wire Interface
- 4 Module Pins
- 5 Electrical Characteristics
- 6 Mechanical Characteristics
- 1
- 7 Application Diagram
- 8 Approvals/Certifications
- 9 Related Documents
- 10 Packing
- 11 Ordering Information
BlueMod+SR/AI
BlueMod+SR/AP
Hardware Reference
Release r04d01 www.stollmann.de Page 13 of 65
3.3 Reset
BlueMod+SR are equipped with circuitry for generating Power ON Reset from the internal core
voltage. A reset is generated when the core voltage falls below typically 1,88V and is released
when it rises above typically 1,92V.
By holding pin B-1 (EXT-RES#) at ≤ 0,5V for ≥ 5ms, an external reset is generated. This pin has a
fixed internal pull-up resistor (R
PU
= 30kΩ ... 50kΩ) and a capacitor to GND (100n) which acts as
debounce filter. If EXT-RES# is not used, it may be left open.
Note:
EXT-RES# pin can also be output. Use an open drain device or push button to drive it low. EXT-
RES# must not be connected to VSUP or driven to logic high-level directly. Provide for an 1kΩ
series resistor when driving EXT-RES# from a CMOS output.
BlueMod+SR
C-1,E-6,F-6
VSUP
GND
+3V3
EXT-RES#
B-1
Reset-Switch is optional
Please Note: BlueMod+SR has an open-drain output and approx. 40k internal pullup
1k
Reset signal is optional
Host MCU
GPIO
VDD
Figure 3: BlueMod+SR Example Reset