Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PLCC 68 16-Bit 20 MHz I/O number 52

TL/DD/8801

HPC16083/HPC26083/HPC36083/HPC46083/HPC16003/HPC26003/

HPC36003/HPC46003 High-Performance microControllers

PRELIMINARY

April 1994

HPC16083/HPC26083/HPC36083/HPC46083/

HPC16003/HPC26003/HPC36003/HPC46003

High-Performance microControllers

General Description

The HPC16083 and HPC16003 are members of the HPC

family of High Performance microControllers. Each member

of the family has the same core CPU with a unique memory

and I/O configuration to suit specific applications. The

HPC16083 has 8k bytes of on-chip ROM. The HPC16003

has no on-chip ROM and is intended for use with external

direct memory. Each part is fabricated in National’s ad-

vanced microCMOS technology. This process combined

with an advanced architecture provides fast, flexible I/O

control, efficient data manipulation, and high speed compu-

tation.

The HPC devices are complete microcomputers on a single

chip. All system timing, internal logic, ROM, RAM, and I/O

are provided on the chip to produce a cost effective solution

for high performance applications. On-chip functions such

as UART, up to eight 16-bit timers with 4 input capture regis-

ters, vectored interrupts, WATCHDOG

logic and MICRO-

WIRE/PLUS

provide a high level of system integration.

The ability to address up to 64k bytes of external memory

enables the HPC to be used in powerful applications typical-

ly performed by microprocessors and expensive peripheral

chips. The term ‘‘HPC16083’’ is used throughout this data-

sheet to refer to the HPC16083 and HPC16003 devices un-

less otherwise specified.

The microCMOS process results in very low current drain

and enables the user to select the optimum speed/power

product for his system. The IDLE and HALT modes provide

further current savings. The HPC is available in 68-pin

PLCC, LDCC, PGA and 80-Pin PQFP packages.

Features

HPC familyÐcore features:

Ð 16-bit architecture, both byte and word

Ð 16-bit data bus, ALU, and registers

Ð 64k bytes of external direct memory addressing

Ð FASTÐ200 ns for fastest instruction when using

20.0 MHz clock, 134 ns at 30 MHz

Ð High code efficiencyÐmost instructions are single

byte

Ð 16 x 16 multiply and 32 x 16 divide

Ð Eight vectored interrupt sources

Ð Four 16-bit timer/counters with 4 synchronous out-

puts and WATCHDOG logic

Ð MICROWIRE/PLUS serial I/O interface

Ð CMOSÐvery low power with two power save modes:

IDLE and HALT

UARTÐfull duplex, programmable baud rate

Four additional 16-bit timer/counters with pulse width

modulated outputs

Four input capture registers

52 general purpose I/O lines (memory mapped)

8k bytes of ROM, 256 bytes of RAM on chip

ROMless version available (HPC16003)

Commercial (0

Cto

C), industrial (

Cto

C), automotive (

Cto

105

C) and military

(

Cto

125

C) temperature ranges

For applications requiring more RAM and ROM see

HPC16064 data sheet.

Block Diagram (HPC16083 with 8k ROM shown)

TL/DD/8801–1

Series 32000

, TapePak

and TRI-STATE

are registered trademarks of National Semiconductor Corporation.

MOLE

, HPC

, COPS

, MICROWIRE/PLUS

and WATCHDOG

are trademarks of National Semiconductor Corporation.

UNIX

is a registered trademarks of AT&T Bell Laboratories.

VAX

is a trademark of Digital Equipment Corporation.

IBM

and PC/AT

are registered trademarks of International Business Machines Corporation.

SUN

is a registered trademark of Sun Microsystems.

SunOS

is a trademark of Sun Microsystems.

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Summary of content (36 pages)

PAGE 1
April 1994 HPC16083/HPC26083/HPC36083/HPC46083/ HPC16003/HPC26003/HPC36003/HPC46003 High-Performance microControllers General Description Features The HPC16083 and HPC16003 are members of the HPCTM family of High Performance microControllers. Each member of the family has the same core CPU with a unique memory and I/O configuration to suit specific applications. The HPC16083 has 8k bytes of on-chip ROM. The HPC16003 has no on-chip ROM and is intended for use with external direct memory.
PAGE 2
Absolute Maximum Ratings VCC with Respect to GND If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Total Allowable Source or Sink Current Storage Temperature Range All Other Pins Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
PAGE 3
20 MHz AC Electrical Characteristics (See Notes 1 and 4 and Figure 1 thru Figure 5 ) VCC e 5.
PAGE 4
20 MHz AC Electrical Characteristics (See Notes 1 and 4 and Figure 1 thru Figure 5 ) VCC e 5.
PAGE 5
30 MHz AC Electrical Characteristics (Continued) (See Notes 1 and 4 and Figure 1 thru Figure 5 ) VCC e 5.
PAGE 6
30 MHz AC Electrical Characteristics (See Notes 1 and 4 and Figure 1 thru Figure 5 ) VCC e 5.
PAGE 7
Timing Waveforms TL/DD/8801 – 33 FIGURE 3. CKI, CK2, ALE Timing Diagram TL/DD/8801 – 3 FIGURE 4. Write Cycle TL/DD/8801 – 4 FIGURE 5. Read Cycle TL/DD/8801 – 5 FIGURE 6.
PAGE 8
Timing Waveforms (Continued) TL/DD/8801 – 6 FIGURE 7. Hold Mode Timing TL/DD/8801 – 37 FIGURE 8. MICROWIRE Setup/Hold Timing TL/DD/8801 – 9 FIGURE 9. UPI Read Timing TL/DD/8801 – 10 FIGURE 10.
PAGE 9
The following is the Military 883 Electrical Specification for HPC16083 and HPC16003. For latest information on RETS 16083X contact NSC local sales office. DC Electrical Specifications Test Conditions VCC e 5V g 10% (Unless Otherwise Specified) (Note 1) Symbol VIH1 Parameter Logical ‘‘1’’ Input Voltage VIH2 VIH3 VIL1 Conditions RESET, NMI, CKI and WO B10 – B13, B15 All Inputs except Port A All Inputs except Port A VIL3 Port A, VCC e 5.5V Port A, VCC e 4.
PAGE 10
AC Electrical Specifications Test Conditions VCC e 4.5V and 5.5V (Unless Otherwise Specified) (Note 1) Symbol Parameter Conditions SBGRP 9 a 25§ C SBGRP 10 a 125§ C Min Max Min fC e CKI Freq.
PAGE 11
AC Electrical Specifications Test Conditions VCC e 4.5V and 5.
PAGE 12
Pin Descriptions (Continued) B14: B15: TS3 RDRDY RDY/HLD has two uses, selected by a software bit. It’s either a READY input to extend the bus cycle for slower memories, or a HOLD request input to put the bus in a high impedance state for DMA purposes. NC (no connection) do not connect anything to this pin. EXM External memory enable (active high) disables internal ROM and maps it to external memory. EI External interrupt with vector address FFF1:FFF0. (Rising/falling edge or high/low level sensitive).
PAGE 13
Connection Diagrams (Continued) Plastic Quad Flatpack TL/DD/8801 – 34 Top View See NS Package Number VJE80A See Part Selection for Ordering Information Pin Grid Array Pinout TL/DD/8801 – 12 Top View (looking down on component side of PC Board) See NS Package Number U68A See Part Selection for Ordering Information 13
PAGE 14
Ports A & B A write operation to a port pin configured as an input causes the value to be written into the data register, a read operation returns the value of the pin. Writing to port pins configured as outputs causes the pins to have the same value, reading the pins returns the value of the data register. Primary and secondary functions are multiplexed onto Port B through the alternate function register (BFUN). The secondary functions are enabled by setting the corresponding bits in the BFUN register.
PAGE 15
Ports A & B (Continued) TL/DD/8801 – 15 FIGURE 13. Structure of Port B Pins B3, B4, B8, B9, B13 and B14 (Timer Synchronous Pins) TL/DD/8801 – 16 FIGURE 14.
PAGE 16
ROM) on-chip. It can address internal memory only, consisting of 8k bytes of ROM (E000 to FFFF) and 256 bytes of onchip RAM and registers (0000 to 01FF). The ‘‘illegal address detection’’ feature of the WATCHDOG is enabled in the Single-Chip Normal mode and a WATCHDOG Output (WO) will occur if an attempt is made to access addresses that are outside of the on-chip ROM and RAM range of the device. Ports A and B are used for I/O functions and not for addressing external memory.
PAGE 17
HPC16003 Operating Modes EXPANDED ROMLESS MODE (HPC16003) Because the HPC16003 has no on-chip ROM, it has only one mode of operation, the Expanded ROMless Mode. The EXM pin must be pulled high (logic ‘‘1’’) on power up, the EA bit in the PSW register should be set to a ‘‘1’’. The HPC16003 is a ROMless device and is intended for use with external memory. The external memory may be any combination of ROM and RAM. Up to 64k bytes of external memory may be accessed.
PAGE 18
HPC16003 Operating Modes (Continued) TL/DD/8801 – 19 FIGURE 17. 16-Bit External Memory IDLE MODE The HPC16083 is placed in the IDLE mode through the PSW. In this mode, all processor activity, except the onboard oscillator and Timer T0, is stopped. As with the HALT mode, the processor is returned to full operation by the RESET or NMI inputs, but without waiting for oscillator stabilization. A timer T0 overflow will also cause the HPC16083 to resume normal operation.
PAGE 19
interrupts may be disabled. IRPD is a Read/Write register. The bits corresponding to the maskable, external interrupts are normally cleared by the HPC16083 after servicing the interrupts. Interrupt Arbitration The HPC16083 contains arbitration logic to determine which interrupt will be serviced first if two or more interrupts occur simultaneously. The arbitration ranking is given in Table III. The interrupt on RESET has the highest rank and is serviced first.
PAGE 20
FIGURE 18.
PAGE 21
Timer Overview software control. Once enabled, the timers count down, and upon underflow, the contents of its associated register are automatically loaded into the timer. The HPC16083 contains a powerful set of flexible timers enabling the HPC16083 to perform extensive timer functions; not usually associated with microcontrollers. The HPC16083 contains nine 16-bit timers. Timer T0 is a free-running timer, counting up at a fixed CKI/16 (Clock Input/16) rate.
PAGE 22
Timer Overview (Continued) TL/DD/8801 – 25 FIGURE 23. Synchronous Pulse Generation WATCHDOG register not be written to before Timer T0 overflows twice, or more often than once every 4096 counts, an infinite loop condition is assumed to have occurred. An illegal condition also occurs when the processor generates an illegal address when in the Single-Chip modes.* Any illegal condition forces the WATCHDOG Output (WO) pin low.
PAGE 23
tem could be used to interface to an instrument cluster and various parts of the automobile. The diagram shows two HPC16083 microcontrollers interconnected to other MICROWIRE peripherals. HPC16083 Ý1 is set up as the master and initiates all data transfers. HPC16083 Ý2 is set up as a slave answering to the master. The master microcontroller interfaces the operator with the system and could also manage the instrument cluster in an automotive application.
PAGE 24
HPC16083 UART The HPC16083 contains a software programmable UART. The UART (see Figure 26 ) consists of a transmit shift register, a receiver shift register and five addressable registers, as follows: a transmit buffer register (TBUF), a receiver buffer register (RBUF), a UART control and status register (ENU), a UART receive control and status register (ENUR) and a UART interrupt and clock source register (ENUI).
PAGE 25
The host uses DMA to interface with the HPC16083. The host initiates a data transfer by activating the HLD input of the HPC16083. In response, the HPC16083 places its system bus in a TRI-STATE Mode, freeing it for use by the host. The host waits for the acknowledge signal (HLDA) from the HPC16083 indicating that the sytem bus is free. On receiving the acknowledge, the host can rapidly transfer data into, or out of, the shared memory by using a conventional DMA controller.
PAGE 26
Shared Memory Support (Continued) TL/DD/8801 – 30 FIGURE 28. Shared Memory Application: HPC16083 Interface to Series 32000 System TABLE IV.
PAGE 27
Design Considerations A recommended crystal oscillator circuit to be used with the HPC is shown below. See table for recommended component values. The recommended values given in the table below have yielded consistent results and are made to match a crystal with a 18 pF load capacitance, with some small allowance for layout capacitance. A recommended layout for the oscillator network should be as close to the processor as physically possible, entirely within 1× distance.
PAGE 28
Indirect HPC16083 CPU The instruction contains an 8-bit address field. The contents of the WORD addressed points to the memory for the operand. Indexed The instruction contains an 8-bit address field and an 8- or 16-bit displacement field. The contents of the WORD addressed is added to the displacement to get the address of the operand. Immediate The instruction contains an 8-bit or 16-bit immediate field that is used as the operand.
PAGE 29
HPC Instruction Set Description (Continued) Mnemonic Description Action BIT INSTRUCTIONS SBIT RBIT IFBIT 1 x Mem.bit 0 x Mem.bit If Mem.bit is true, do next instr.
PAGE 30
Memory Usage Number Of Bytes For Each Instruction (number in parenthesis is 16-Bit field) Using Accumulator A Reg Indir. (B) (X) Direct To Direct Memory Indir. Index Immed. Direct Immed.
PAGE 31
Code Efficiency One of the most important criteria of a single chip microcontroller is code efficiency. The more efficient the code, the more features that can be put on a chip. The memory size on a chip is fixed so if code is not efficient, features may have to be sacrificed or the programmer may have to buy a larger, more expensive version of the chip. The HPC16083 has been designed to be extremely codeefficient.
PAGE 32
Development Support (Continued) ment for accessing Dial-A-Helper is a Hayes compatible modem. DIAL-A-HELPER Dial-A-Helper is a service provided by the Microcontroller Applications group. Dial-A-Helper is an Electronic Bulletin Board Information system and additionally, provides the capability of remotely accessing the development system at a customer site. If the user has a PC with a communications package then files from the FILE SECTION can be down loaded to disk for later use.
PAGE 33
Development Support (Continued) Voice: (408) 721-5582 Modem: (408) 739-1162 Baud: 300 or 1200 Baud Set-Up: Length: 8-bit Parity: None Stop Bit: 1 Operation: 24 hrs, 7 days DIAL-A-HELPER TL/DD/8801 – 32 Part Selection The HPC family includes devices with many different options and configurations to meet various application needs. The number HPC16083 has been generically used throughout this datasheet to represent the whole family of parts.
PAGE 34
Physical Dimensions inches (millimeters) Leaded Chip Carrier Package (EL) Order Number HPC16083XXX/L20, HPC16083XXX/L30, HPC16003EL20, HPC26003EL20, HPC36003EL20, HPC46003EL20, HPC16003EL30, HPC26003EL30, HPC36003EL30 or HPC46003EL30 NS Package Number EL68A Pin Grid Array Pinout (U) Order Number HPC16083XXX/U20, HPC16083XXX/U30, HPC16003U20 or HPC16003U30 NS Package Number U68A 34
PAGE 35
Physical Dimensions inches (millimeters) (Continued) Plastic Leaded Chip Carrier (V) Order Number HPC16083XXX/V20, HPC26083XXX/V20, HPC36083XXX/V20, HPC46083XXX/V20, HPC16083XXX/V30, HPC26083XXX/V30, HPC36083XXX/V30, HPC16083XXX/V30, HPC16003V20, HPC26003V20, HPC36003V20, HPC46003V20, HPC16003V30, HPC26003V30, HPC36003V30 or HPC46003V30 NS Package Number V68A 35
PAGE 36
HPC16083/HPC26083/HPC36083/HPC46083/HPC16003/HPC26003/ HPC36003/HPC46003 High-Performance microControllers Physical Dimensions inches (millimeters) (Continued) 80-Pin QFP Package (VF) Order Number HPC46083XXX/F20, HPC46083XXX/F30, HPC46003VF20 or HPC46003VF30 NS Package Number VF80B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION.