Datasheet

MICROWIRE/PLUS Operation

The HPC16083 can enter the MICROWIRE/PLUS mode as

the master or a slave. A control bit in the IRCD register

determines whether the HPC16083 is the master or slave.

The shift clock is generated when the HPC16083 is config-

ured as a master. An externally generated shift clock on the

SK pin is used when the HPC16083 is configured as a slave.

When the HPC16083 is a master, the DIVBY register pro-

grams the frequency of the SK clock. The DIVBY register

allows the SK clock frequency to be programmed in 15 se-

lectable steps from 64 Hz to 1 MHz with CKI at 16.0 MHz.

The contents of the SIO register may be accessed through

any of the memory access instructions. Data waiting to be

transmitted in the SIO register is clocked out on the falling

edge of the SK clock. Serial data on the SI pin is clocked in

on the rising edge of the SK clock.

MICROWIRE/PLUS Application

Figure 25

illustrates a MICROWIRE/PLUS arrangement for

an automotive application. The microcontroller-based sys-

tem could be used to interface to an instrument cluster and

various parts of the automobile. The diagram shows two

HPC16083 microcontrollers interconnected to other MI-

CROWIRE peripherals. HPC16083

1 is set up as the mas-

ter and initiates all data transfers. HPC16083

2 is set up

as a slave answering to the master.

The master microcontroller interfaces the operator with the

system and could also manage the instrument cluster in an

automotive application. Information is visually presented to

the operator by means of a LCD display controlled by the

COP472 display driver. The data to be displayed is sent

serially to the COP472 over the MICROWIRE/PLUS link.

Data such as accumulated mileage could be stored and re-

trieved from the EEPROM COP494. The slave HPC16083

could be used as a fuel injection processor and generate

timing signals required to operate the fuel valves. The mas-

ter processor could be used to periodically send updated

values to the slave via the MICROWIRE/PLUS link. To

speed up the response, chip select logic is implemented by

connecting an output from the master to the external inter-

rupt input on the slave.

TL/DD/8801–27

FIGURE 25. MICROWIRE/PLUS Application