Datasheet

Universal Peripheral Interface
The Universal Peripheral Interface (UPI) allows the
HPC16083 to be used as an intelligent peripheral to another
processor. The UPI could thus be used to tightly link two
HPC16083’s and set up systems with very high data ex-
change rates. Another area of application could be where a
HPC16083 is programmed as an intelligent peripheral to a
host system such as the Series 32000
É
microprocessor.
Figure 27 illustrates how a HPC16083 could be used an an
intelligent peripherial for a Series 32000-based application.
The interface consists of a Data Bus (port A), a Read Strobe
(URD
), a Write Strobe (UWR), a Read Ready Line (RDRDY),
a Write Ready Line (WRRDY
) and one Address Input (UA0).
The data bus can be either eight or sixteen bits wide.
The URD
and UWR inputs may be used to interrupt the
HPC16083. The RDRDY
and WRRDY outputs may be used
to interrupt the host processor.
The UPI contains an Input Buffer (IBUF), an Output Buffer
(OBUF) and a Control Register (UPIC). In the UPI mode,
port A on the HPC16083 is the data bus. UPI can only be
used if the HPC16083 is in the Single-Chip mode.
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data. It is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block. The HPC16083
supports shared memory access with two pins. The pins are
the RDY/HLD
input pin and the HLDA output pin. The user
can software select either the Hold or Ready function by the
state of a control bit. The HLDA
output is multiplexed onto
port B.
The host uses DMA to interface with the HPC16083. The
host initiates a data transfer by activating the HLD
input of
the HPC16083. In response, the HPC16083 places its sys-
tem bus in a TRI-STATE Mode, freeing it for use by the host.
The host waits for the acknowledge signal (HLDA
) from the
HPC16083 indicating that the sytem bus is free. On receiv-
ing the acknowledge, the host can rapidly transfer data into,
or out of, the shared memory by using a conventional DMA
controller. Upon completion of the message transfer, the
host removes the HOLD request and the HPC16083 re-
sumes normal operations.
Figure 28 illustrates an application of the shared memory
interface between the HPC16083 and a Series 32000 sys-
tem. To insure proper operation, the interface logic shown is
recommended as the means for enabling and disabling the
user’s bus.
Memory
The HPC16083 has been designed to offer flexibility in
memory usage. A total address space of 64 kbytes can be
addressed with 8 kbytes of ROM and 256 bytes of RAM
available on the chip itself. The ROM may contain program
instructions, constants or data. The ROM and RAM share
the same address space allowing instructions to be execut-
ed out of RAM.
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis. Memory can be addressed
directly by instructions or indirectly through the B, X and SP
registers. Memory can be addressed as words or bytes.
Words are always addressed on even-byte boundaries. The
HPC16083 uses memory-mapped organization to support
registers, I/O and on-chip peripheral functions.
The HPC16083 memory address space extends to 64
kbytes and registers and I/O are mapped as shown in Table
IV.
TL/DD/8801–29
FIGURE 27. HPC16083 as a Peripheral: (UPI Interface to Series 32000 Application)
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