Datasheet

20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 thru Figure 5 )V
CC
e
5.0V
g
10% unless otherwise specified, T
A
e
0
§
Cto
a
70
§
C for
HPC46083/HPC46003,
b
40
§
Cto
a
85
§
C for HPC36083/HPC36003,
b
40
§
Cto
a
105
§
C for HPC26083/HPC26003,
b
55
§
Cto
a
125
§
C for HPC16083/HPC16003
Symbol and Formula Parameter Min Max Units Note
f
C
CKI Operating Frequency 2 20 MHz
t
C1
e
1/f
C
CKI Clock Period 50 500 ns
t
CKIH
CKI High Time 22.5 ns
t
CKIL
CKI Low Time 22.5 ns
t
C
e
2/f
C
CPU Timing Cycle 100 ns
t
WAIT
e
t
C
CPU Wait State Period 100 ns
t
DC1C2R
Delay of CK2 Rising Edge after
0 55 ns (Note 2)
CKI Falling Edge
t
DC1C2F
Delay of CK2 Falling Edge after
0 55 ns (Note 2)
CKI Falling Edge
f
U
e
f
C
/8 External UART Clock Input Frequency 2.5** MHz
f
MW
External MICROWIRE/PLUS
1.25 MHz
Clock Input Frequency
f
XIN
e
f
C
/22 External Timer Input Frequency 0.91 MHz
t
XIN
e
t
C
Pulse Width for Timer Inputs 100 ns
t
UWS
MICROWIRE Setup TimeÐMaster 100 ns
ÐSlave 20
t
UWH
MICROWIRE Hold TimeÐMaster 20 ns
ÐSlave 50
t
UWV
MICROWIRE Output Valid TimeÐMaster 50 ns
ÐSlave 150
t
SALE
e
*/4 t
C
a
40 HLD Falling Edge before ALE Rising Edge 115 ns
t
HWP
e
t
C
a
10 HLD Pulse Width 110 ns
t
HAE
e
t
C
a
100 HLDA Falling Edge after HLD Falling Edge 200 ns (Note 3)
t
HAD
e
*/4 t
C
a
85 HLDA Rising Edge after HLD Rising Edge 160 ns
t
BF
e
(/2 t
C
a
66 Bus Float after HLDA Falling Edge 116 ns (Note 5)
t
BE
e
(/2 t
C
a
66 Bus Enable after HLDA Rising Edge 116 ns (Note 5)
t
UAS
Address Setup Time to Falling Edge of URD 10 ns
t
UAH
Address Hold Time from Rising Edge of URD 10 ns
t
RPW
URD Pulse Width 100 ns
t
OE
URD Falling Edge to Output Data Valid 0 60 ns
t
OD
Rising Edge of URD to Output Data Invalid 5 35 ns (Note 6)
t
DRDY
RDRDY Delay from Rising Edge of URD 70 ns
t
WDW
UWR Pulse Width 40 ns
t
UDS
Input Data Valid before Rising Edge of UWR 10 ns
t
UDH
Input Data Hold after Rising Edge of UWR 20 ns
t
A
WRRDY Delay from Rising Edge of UWR 70 ns
ClocksTimers
MICROWIRE/
PLUS
External HoldUPI Timing
**This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
3