TMS320C645x Serial Rapid IO (SRIO) User's Guide Literature Number: SPRU976 March 2006
SPRU976 – March 2006 Submit Documentation Feedback
Contents Preface.............................................................................................................................. 13 1 Overview .................................................................................................................. 14 2 3 4 5 1.1 General RapidIO System ......................................................................................... 14 1.2 RapidIO Feature Support in SRIO ..................................................................
5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) .................. 126 5.26 DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) .............................. 127 5.27 DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) 128 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) 129 5.29 5.30 5.31 5.32 5.33 5.34 5.35 4 .......................... .......................................
.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ................................... 174 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) ..................................... 175 5.74 Base Device ID CSR (BASE_ID) .............................................................................. 176 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) 5.76 5.77 5.78 5.79 5.80 5.81 5.82 5.83 5.84 5.85 5.86 5.87 5.88 5.89 5.90 5.91 5.92 5.93 5.94 5.95 5.96 5.97 5.98 5.99 5.
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 6 RapidIO Architectural Hierarchy .......................................................................................... RapidIO Interconnect Architecture ....................................................................................... Serial RapidIO Device to Device Interface Diagrams .....................................................
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Load/Store Module Interrupt Condition Routing Registers............................................................ 82 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 83 Sharing of ISDR Bits .........................................................................................
105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 8 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) .......................... Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) .................................. Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) .........................
158 159 160 161 162 163 164 165 166 167 Port Error Rate Threshold CSR n (SPn_ERR_THRESH) ........................................................... Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) .............................................. Port IP Mode CSR (SP_IP_MODE) .................................................................................... Serial Port IP Prescalar (IP_PRESCAL) ...............................................................................
List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 10 RapidIO Documents and Links ........................................................................................... 18 Packet Type ................................................................................................................. 23 Pin Description.......................................................................................
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions ......................................... TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions .......................................... LSU Status Interrupt Register (LSU_ICSR) Field Descriptions .....................................................
99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 12 Source Operations CAR (SRC_OP) Field Descriptions ............................................................. Destination Operations CAR (DEST_OP) Field Descriptions ....................................................... Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions ..............................
Preface SPRU976 – March 2006 Read This First About This Manual This document describes the Serial Rapid IO (SRIO) on the TMS320C645x devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
User's Guide SPRU976 – March 2006 Serial RapidIO (SRIO) 1 Overview The RapidIO peripheral used in the TMS320C645x is called a serial RapidIO (SRIO). This chapter describes the general operation of a RapidIO system, how this module is connected to the outside world, the definitions of terms used within this document, and the features supported and not supported for SRIO. 1.1 General RapidIO System RapidIO™ is a non-proprietary high-bandwidth system level interconnect.
www.ti.com Overview Figure 1. RapidIO Architectural Hierarchy Logical specification Information necessary for the end point to process the transaction (i.e., transaction type, size, physical address) I/O system Transport specification Information to transport packet from end to end in the system (i.e., routing address) Physical specification Information necessary to move packet between two physical devices (i.e.
www.ti.com Overview 1.1.2 RapidIO Interconnect Architecture The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation. Figure 2 illustrates the interconnection system. Figure 2.
www.ti.com Overview Figure 3. Serial RapidIO Device to Device Interface Diagrams 1x Device 1x Device TD[0] RD[0] TD[0] RD[0] RD[0] TD[0] RD[0] TD[0] Serial RapidIO 1x Device to 1x Device Interface Diagram 4x Device 4x Device TD[0-3] RD[0-3] TD[0-3] RD[0-3] RD[0-3] TD[0-3] RD[0-3] TD[0-3] Serial RapidIO 4x Device to 4x Device Interface Diagram 1.2 RapidIO Feature Support in SRIO Features Supported in SRIO: • RapidIO Interconnect Specification V1.2 compliance, Errata 1.
www.ti.com Overview Features Not Supported: • Compliance with the Global Shared Memory specification (GSM) • 8/16 LP-LVDS compatible • Destination support of RapidIO Atomic Operations • Simultaneous mixing of frequencies between 1X ports (all ports must be the same frequency) • Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal L2 memory and registers 1.3 Standards The SRIO peripheral is compliant to V1.
www.ti.com SRIO Functional Description 2 SRIO Functional Description 2.1 Overview 2.1.1 Peripheral Data Flow This peripheral is designed to be an external slave module that is capable of mastering the internal DMA. This means that an external device can push (burst write) data to the DSP as needed, without having to generate an interrupt to the CPU. This has two benefits. It cuts down on the total number of interrupts, and it reduces handshaking (latency) associated with read-only peripherals.
www.ti.
www.ti.com SRIO Functional Description SRIO endpoints are typically not connected directly to each other but instead have intervening connection fabric devices. Control symbols are used to manage the flow of transactions in the SRIO physical interconnect. Control symbols are used for packet acknowledgment, flow control information, and maintenance functions. Figure 5 shows how a packet progresses through the system. Figure 5.
www.ti.com SRIO Functional Description Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) n*64+80 PHY acklD rsv 5 3 prio tt ftype destID 2 2 8 4 29 8 1 TRA LOG 16 n*64+32 4 address rsrv xamsbs sourcelD LOG TRA 2 10 ...
www.ti.com SRIO Functional Description The type of received packet determines how the packet routing is handled. Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous allocation of resources to them. Unsupported packet types are responded to with an error response packet. Section 2.1.2.4 details the handling of such packets. 2.1.2.
www.ti.com SRIO Functional Description 2.2 SRIO Pins The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching levels. The transmit and receive buffers are self-contained within the clock recovery blocks. The reference clock input is not incorporated into the SERDES macro. It uses a common LVDS input buffer that aligns interfaces with crystal oscillator manufacturers. None of the peripheral pins may be used as GPIO pins. Table 3 provides more detail. Table 3.
www.ti.com SRIO Functional Description Figure 8. SRIO Conceptual Block Diagram DMA bus 128-bit Load/store unit (LSU) Tx direct I/O TXU Messaging Maintenance 4.5 KB Tx shared buffer Memory access unit (MAU) Rx direct I/O RXU Messaging 4.
www.ti.com SRIO Functional Description 2.3.2 SERDES and its Configurations SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can be used for all three frequency nodes specified in V1.2 of the RapidIO specification (1.25, 2.5, and 3.125 Gbps).
www.ti.com SRIO Functional Description Table 4. Bits of SERDES_CFGn_CNTL Register (0x120 - 0x12c) (continued) Bit Name 5:1 MPY 0 Value Description PLL multiply. Select PLL multiply factors between 4 and 60. Multiply modes shown below. 0000 4x 0001 5x 0010 6x 0011 Reserved 0100 8x 0101 10x 0110 12x 0111 12.5x 1000 15x 1001 20x 1010 25x 1011 Reserved 1100 Reserved 1101 50x 1110 60x 1111 Reserved ENPLL Enable PLL. Enables the PLL.
www.ti.com SRIO Functional Description Here is the frequency range versus MPY: Table 7. Frequency Range versus MPY MPY RIOCLK and RIOCLK Line Rate Range (Gbps) Range (MHz) Full Half Quarter 250 - 425 2 - 3.4 1 - 1.7 0.5 - 0.85 5x 200 - 425 2 - 4.25 1 - 2.125 0.5 - 1.0625 6x 167 - 354.167 2 - 4.25 1 - 2.125 0.5 - 1.0625 8x 125 - 265.625 2 - 4.25 1 - 2.125 0.5 - 1.0625 10x 100 - 212.5 2 - 4.25 1 - 2.125 0.5 - 1.0625 4x 12x 83.33 - 177.08 2 - 4.25 1 - 2.125 0.5 - 1.
www.ti.com SRIO Functional Description Table 8. Bits of SERDES_CFGRXn_CNTL Registers (continued) Bit Field 15:14 LOS 13:12 Value Description Loss of signal. Enables loss of signal detection with 2 selectable thresholds. 00 Disabled. Loss of signal detection disabled. 01 High threshold. Loss of signal detection threshold in the range 85 to 195mVdfpp. This setting is suitable for Infiniband. 10 Low threshold. Loss of signal detection threshold in the range 65-175mVdfpp.
www.ti.com SRIO Functional Description Table 9. EQ Bits 2.3.2.3 CFGRX[22:19] Low Freq Gain Zero Freq (at e28 (min)) 0000 Maximum - 0001 Adaptive Adaptive 001x Reserved 01xx Reserved 1000 Adaptive 1084MHz 1001 805MHz 1010 573MHz 1011 402MHz 1100 304MHz 1101 216MHz 1110 156MHz 1111 135MHz Enabling the Transmitter To enable a transmitter for serialization, the ENTX bit of the associated SERDES_CFGTXn_CNTL registers (0x110 – 0x10c) must be set high.
www.ti.com SRIO Functional Description Table 10. Bits of SERDES_CFGTXn_CNTL Registers (continued) Bit Field 4:2 BUSWIDTH Value Description Bus width. Selects the width of the parallel interface (10 or 8 bit). 000 10-bit operation. Data is input on TDn[9:0]. TXBCLKn period is 10 bit periods (4 high, 6 low). 001 8-bit operation. Data is input on TDn[9:2]. TXBCLKn period is 8 bit periods (4 high, 4 low). TDn[1:0] are ignored.
www.ti.com SRIO Functional Description 2.3.2.
www.ti.com SRIO Functional Description Figure 10.
www.ti.com SRIO Functional Description Table 13. Control/Command Register Field Mapping (continued) Control/Command Register Field RapidIO Packet Header Field Packet Type 4 msb = 4b ftype field for all packets and 4 lsb = 4b trans field for packet types 2,5,8. OutPortID Not available in RapidIO header. Indicates the output port number for the packet to be transmitted from. Specified by the CPU along with NodeID. Drbll Info RapidIO doorbell info field for type 10 packets.
www.ti.com SRIO Functional Description Figure 11. LSU Registers Timing T0 T1 T2 T3 T4 After Transaction Completes Tn T5 Valid LSU_Reg1 Valid LSU_Reg2 LSU_Reg3 Valid LSU_Reg4 Valid LSU_Reg5 Valid Rdy/BSY Completion Valid Valid The following code illustrates an LSU registers programming example.
www.ti.com SRIO Functional Description Figure 12.
www.ti.com SRIO Functional Description Figure 13. Load/Store Module Data Flow UDI interface RapidIO transport and physical layers Peripheral boundary Load/store module Write transfer descriptors Port x transmission FIFO queues I/O pins Control and arbitrator TX FIFO RX FIFO Response timer LSU4 LSU3 LSU2 LSU1 MMR command Shared TX data Config bus access CPU DMA request Shared RX data L2 memory DMA response = Shared resource for CPPI and MAU 2.3.3.
www.ti.com SRIO Functional Description For posted WRITE operations, which do not require a RapidIO response packet, a core may submit multiple outstanding requests. For instance, a single core may have many streaming write packets buffered at any given time, given outgoing resources. In this application, the control/command registers can be released (BSY = 0) to the CPU as soon as the header info is written into the shared TX buffer pool.
www.ti.com SRIO Functional Description Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4KB). The second type is when Read/Write request RapidIO address is non-64b aligned. In both cases, the outgoing request must be broken up into multiple RapidIO request packets. For example, assume that the CPU wants to perform a 1KB store operation to an external RapidIO device.
www.ti.
www.ti.com SRIO Functional Description 2.3.4.1 RX Operation As message packets are received by the RapidIO ports, the data must be written into memory while maintaining accurate state information that is needed for future processing. For instance, if a message spans multiple packets, information must be saved that allows re-assembly of those packets by the CPU. The CPPI module provides a scheme for tracking single and multi-packet messages, linking messages in queues, and generating interrupts.
www.ti.com SRIO Functional Description This allows the letter and mailbox fields to instead allow four concurrent single-segment messages to sixty-four possible mailboxes (256 total locations) for a source and destination pair. The mailbox mapper directs the inbound messages to the appropriate queue based on a pre-programmed routing table. It bases the decision on the SOURCEID, MSGLEN, MBOX, LETTER, and XMBOX fields of the RapidIO packet.
www.ti.com SRIO Functional Description Figure 17. Queue Mapping Register RXU_MAP_Ln 31 30 29 24 23 22 21 16 Letter Mask Mailbox Mask Letter Mailbox R/W-11 R/W-111111 R/W-0 R/W-000000 15 0 SOURCEID R/W-0x0000 LEGEND: R = Read, W = Write, n = value at reset Figure 18.
www.ti.com SRIO Functional Description If a multi-segment buffer descriptor queue is not currently free, and an Rx port receives another multi-segment message that is destined for that queue, the RX CPPI must send a RETRY RESPONSE packet (Type 13) to the sender, indicating that an internal buffering problem exists. If a multi-segment buffer descriptor queue is busy and there is another incoming multi-segment message with the same SOURCEID, MAILBOX, and LETTER, an ERROR response is sent.
www.ti.com SRIO Functional Description Table 17. RX Buffer Descriptor Field Descriptions Field Description next_descriptor_pointer Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer descriptor in the RX queue. This references the next buffer descriptor from the current buffer descriptor. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The host sets the next_descriptor_pointer.
www.ti.com SRIO Functional Description Table 17. RX Buffer Descriptor Field Descriptions (continued) Field Description mailbox Destination Mailbox: Specifies the mailbox to which the message was sent. 000000b: Mailbox 0 000001b: Mailbox 1 ... 000100b: Mailbox 4 ... 111111b: Mailbox 63 For multi-segment messages, only the two LSBs of this mailbox are valid. Hardware ignores the four MSBs if the incoming message has multiple segments.
www.ti.com SRIO Functional Description Figure 20.
www.ti.com SRIO Functional Description Teardown of an Rx queue causes the following actions: • If teardown is issued by software during the time when the RX state machine is idle, then the state machine will immediately start the teardown procedure: – If the queue to be torn down is in-message (waiting for one or more segments), then the queue will be torn down and reported with the current buffer descriptor (teardown bit set, ownership bit cleared, CC = 100b).
www.ti.com SRIO Functional Description 2.3.4.2 TX Operation Outgoing messages are handled similarly, with buffer descriptor queues that are assigned by the CPUs. The queues are configured and initialized upon reset. When a CPU wants to send a message to an external RapidIO device, it writes the buffer descriptor information via the configuration bus into the SRAM. Again, there is a single buffer descriptor per RapidIO message.
www.ti.com SRIO Functional Description Table 20. TX Buffer Descriptor Field Definitions (continued) Field Description ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is set by the host and cleared by the port when the message has been transmitted. The host uses this bit to reclaim buffers.
www.ti.com SRIO Functional Description Table 20. TX Buffer Descriptor Field Definitions (continued) Field Description tt RapidIO tt field specifying 8- or 16-bit DeviceIDs 00: 8b deviceIDs 01: 16b deviceIDs 10: reserved 11: reserved PortID Port number for routing outgoing packet. SSIZE RIO standard message payload size. Indicates how the hardware should segment the outgoing message by specifying the maximum number of double-words per packet.
www.ti.com SRIO Functional Description Figure 23.
www.ti.com SRIO Functional Description Table 21.
www.ti.com SRIO Functional Description Essentially, instead of the 24-bit value representing the period of the response timer, the period is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 – 89.5Mhz for a 6 – 3 second response timeout. Since the needed timer frequency is derived from the DMA bus clock (which is device dependent), the hardware supports a programmable configuration register field to properly scale the clock frequency.
www.ti.com SRIO Functional Description The CPPI module can be powered down if the message passing protocol is not being supported in the application. For example, if the direct I/O protocol is being used for data transfers, powering down the CPPI module will save power. In this situation, the buffer descriptor queue SRAMs and mailbox mapper logic should be powered down. Clocks should be gated to these blocks while in the power down state. Section 2.3.9 describes this in detail. 2.3.4.
www.ti.com SRIO Functional Description • This value is compared against the port written value in the TX DMA State CP register, if equal, the interrupt is deasserted.
www.ti.com SRIO Functional Description Figure 24.
www.ti.com SRIO Functional Description Figure 25. TX Buffer Descriptor Descriptor Buffer Descriptor Buffer Tx Queue Head Descriptor Pointer Port Tx DMA State Start Message Passing SRIO_REGS->Queue0_RXDMA_HDP SRIO_REGS->Queue0_TxDMA_HDP 2.3.5 = (int )RX_DESCP0_0 ; = (int )TX_DESCP0_0 ; Maintenance The type 8 MAINTENANCE packet format accesses the RapidIO capability registers (CARs), command and status registers (CSRs), and data structures.
www.ti.com SRIO Functional Description 2.3.6 Doorbell The doorbell operation, consisting of the DOORBELL and RESPONSE transactions (typically a DONE response), as shown in Figure 26, is used by a processing element to send a very short message to another processing element through the interconnect fabric. The DOORBELL transaction contains the info field to hold information and does not have a data payload. This field is software-defined and can be used for any desired purpose; see Section 3.1.
www.ti.com SRIO Functional Description 2.3.7 Congestion Control The RapidIO Flow Control specification is referenced in Table 1. This section describes the requirements and implementation of congestion control within the peripheral. The peripheral is notified of switch fabric congestion through type 7 RapidIO packets. The packets are referred to as Congestion Control Packets (CCPs).
www.ti.com SRIO Functional Description Figure 27. Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) RIO_FLOW_CNTL0 RIO_FLOW_CNTL1 RIO_FLOW_CNTL2 RIO_FLOW_CNTL15 31 17 15 Reserved tt Flow_Cntl_ID0 R, all zeros R/W, 0b01 R/W, 0x0000 31 17 15 Reserved tt Flow_Cntl_ID1 R, all zeros R/W, 0b01 R/W, 0x0000 31 17 15 Reserved tt Flow_Cntl_ID2 R, all zeros R/W, 0b01 R/W, 0x0000 31 17 15 Reserved tt Flow_Cntl_ID15 R, all zeros R/W, 0b01 R/W, 0x0000 Table 22.
www.ti.com SRIO Functional Description Figure 28.
www.ti.com SRIO Functional Description 2.3.8 Endianness RapidIO is based on big endian. This is discussed in detail in section 2.4 of the RapidIO Interconnect specification. Essentially, big endian specifies the address ordering as the most significant bit/byte first. For example, in the 29-bit address field of a RapidIO packet (shown in Figure 6) the left-most bit that is transmitted first in the serial bit stream is the MSB of the address.
www.ti.com SRIO Functional Description Figure 30. DMA Example DMA Example The desired operation is to send a Type 8 maintenance request to an external device. The goal is to read 16B of RapidIO MMR from an external device, starting offset 0x0000. This operation involves the LSU block and utilizes the DMA for transferring the response packet payload.
www.ti.com SRIO Functional Description 2.3.9.1 Reset Summary After reset, the state of the peripheral depends on the default register values and the BLKn_EN_INIT tieoff values. You can also perform a hard reset using the software of each logical block within the peripheral via the GBL_EN and BLKn_EN bits. The GBL_EN bits reset the peripheral, while the rest of the device is not reset. The BLKn_EN bits shut down unused portions of the peripheral.
www.ti.com SRIO Functional Description Figure 34. BLK0_EN_STAT (Address 0x003C) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, n = value at reset Figure 35. BLK1_EN (Address 0x0040) 31 1 0 Reserved EN R-0 R/W-1 LEGEND: R = Read, W = Write, n = value at reset Figure 36. BLK1_EN_STAT (Address 0x0044) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, n = value at reset • • • Figure 37.
www.ti.com SRIO Functional Description Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name Bit Access BLK1_EN 0 R/W Description Controls reset to logical block 1, which is the LSU. 0 = Logical block 1 disabled (held in reset, clocks disabled) 1 = Logical block 1 enabled BLK1_EN_STAT 0 R Indicates state of BLK1_EN reset signal.
www.ti.com SRIO Functional Description Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name Bit Access BLK8_EN_STAT 0 R Description Indicates state of BLK8_EN reset signal. 0 = Logical block 8 in reset and clock is off 1 = Logical block 8 enabled and clocking The GBL_EN register is implemented with a single ENABLE bit. This bit is logically ORd with the reset input to the module and is fanned out to all logical blocks within the peripheral. 2.3.9.
www.ti.com SRIO Functional Description Table 25. Emulation Control Signals Name Bit Access Reset Value Free 0 R/W 1b Description FREE = 0, SOFT Bit takes effect FREE = 1, Free run mode (default mode) - Peripheral ignores the EMUSUSP signal and functions normally. Soft 1 R/W 0b SOFT = 0 -> Soft Stop (default mode) SOFT = 1 -> Hard stop – All status registers are frozen in default state. (Mode not supported) PEREN 2 R/W 0b Peripheral Enable.
www.ti.com SRIO Functional Description 2.3.11.2 PLL, Ports, Device ID and Data Rate Initializations For example, Enable pll, 333MHz, 4p1x, x20. 3.
www.ti.
www.ti.com SRIO Functional Description 2.3.12 Bootload Capability 2.3.12.1 Configuration It is assumed that an external device will initiate the bootload data transfer and master the DMA interface. Upon reset, the following sequence of events must occur: 1. DSP is placed in SRIO boot mode by HW mode pins. 2. Host takes DSP out of reset (POR or RST). The peripheral’s state machines and registers are reset. 3. Internal boot-strap ROM configures device registers, including SERDES, and DMA.
www.ti.com Logical/Transport Error Handling and Logging 3 Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors. Figure 41 illustrates the detectable errors. Figure 41.
www.ti.com Interrupt Conditions 4 Interrupt Conditions This section defines the CPU interrupt capabilities and requirements of the peripheral. 4.1 CPU Interrupts The following interrupts are supported by the RIO peripheral. • Error Status: Event indicating that a run-time error was reached. The CPU should reset/resynchronize the peripheral. • Critical Error: Event indicating that a critical error state was reached. The CPU should reset the system.
www.ti.com Interrupt Conditions The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers. Each bit can be assigned to any core as described by the Interrupt Condition Routing Registers. Additionally, each status bit is user-defined for the application.
www.ti.com Interrupt Conditions Table 26. Interrupt Source Configuration Options Field Access Reset Value Value ICSx R 0 0b Condition not present 1b Condition present 0b No effect 1b Condition status cleared ICCx W 0 Function Figure 43.
www.ti.com Interrupt Conditions Where ICS0 - Doorbell1, bit 0, through ICS15 - Doorbell1, bit 15. Figure 45.
www.ti.com Interrupt Conditions Figure 47.
www.ti.com Interrupt Conditions Where ICS0 - TX CPPI interrupt, buffer descriptor queue 0, through ICS15 - TX CPPI interrupt, buffer descriptor queue 15. Clearing of any ICSR bit is dependent on the CPU writing to the TX DMA State CP. The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value. This value is compared against the port written value in the TX DMA State CP register. If equal, the interrupt is deasserted. Figure 49.
www.ti.
www.ti.com Interrupt Conditions The interrupt conditions are programmable to select the interrupt output that will be driven. Each condition is independently programmable to use any of the interrupt destinations supported by the device. For example, a quad core device may support four CPU servicing interrupt destinations, one per core (INTDST0 for Core0, INTDST1 for Core1, INTDST2 for Core2, and INTDST3 for Core3).
www.ti.com Interrupt Conditions Figure 52.
www.ti.com Interrupt Conditions Figure 53.
www.ti.com Interrupt Conditions Figure 54. Sharing of ISDR Bits ISDR bits: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 LSU Error, reset and special event Tx CPPI [15:0] Rx CPPI [15:0] ISDR bits: 15 14 13 12 11 10 9 8 7 Doorbell 0 [15:0] Doorbell 1 [15:0] Doorbell 2 [15:0] Doorbell 3 [15:0] As an example, if bit 29 of the ISDR is set, this indicates that there is a pending interrupt on either the TX CPPI queue 2 or RX CPPI queue 2.
www.ti.com Interrupt Conditions LSU bits within the ICSR are logically grouped for a given core and ORd together into a single bit of the decode register. Similarly, the Error/Reset/Special event bits within the ICSR are ORd together into a single bit of the decode register. When either of these bits are set in the decode register, the CPU must make additional reads to the corresponding ICSRs to determine that exact interrupt source.
www.ti.com Interrupt Conditions Figure 57. INTDSTn_RATE_CNTL Interrupt Rate Control Register 31 0 32-bit Count Down Value R/W-0 LEGEND: R = Read, W = Write, n = value at reset Offsets: • INTDST0 – • INTDST1 – • INTDST2 – • INTDST3 – • INTDST4 – • INTDST5 – • INTDST6 – • INTDST7 – 4.7 0x0320 0x0324 0x0328 0x032C 0x0330 0x0334 0x0338 0x033C Interrupt Handling Interrupts are either signaled externally through RapidIO packets, or internally by state machines in the peripheral.
www.ti.
www.ti.com SRIO Registers 5 SRIO Registers 5.1 Introduction Table 28 lists the memory-mapped registers for the Serial Rapid IO (SRIO). See the device-specific data manual for the memory address of these registers. Table 28. Serial Rapid IO (SRIO) Registers 88 Offset Acronym Register Description Section 0x0000 PID Peripheral Identification Register Section 5.2 0x0004 PCR Peripheral Control Register Section 5.3 0x0020 PER_SET_CNTL Peripheral Settings Control Register Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description 0x0110 SERDES_CFGTX0_ CNTL SERDES Transmit Channel Configuration Register 0 Section 5.14 0x0114 SERDES_CFGTX1_ CNTL SERDES Transmit Channel Configuration Register 1 Section 5.14 0x0118 SERDES_CFGTX2_ CNTL SERDES Transmit Channel Configuration Register 2 Section 5.14 0x011C SERDES_CFGTX3_ CNTL SERDES Transmit Channel Configuration Register 3 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset 90 Acronym Register Description 0x02EC LSU_ICRR3 LSU Interrupt Condition Routing Register 3 Section 5.35 Section 0x02F0 ERR_RST_EVNT_IC RR Error, Reset, and Special Event Interrupt Condition Routing Register Section 5.36 0x02F4 ERR_RST_EVNT_IC RR2 Error, Reset, and Special Event Interrupt Condition Routing Register 2 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description 0x0444 LSU3_REG1 LSU3 Control Register 1 Section 5.42 Section 0x0448 LSU3_REG2 LSU3 Control Register 2 Section 5.43 0x044C LSU3_REG3 LSU3 Control Register 3 Section 5.44 0x0450 LSU3_REG4 LSU3 Control Register 4 Section 5.45 0x0454 LSU3_REG5 LSU3 Control Register 5 Section 5.46 0x0458 LSU3_REG6 LSU3 Control Register 6 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) 92 Offset Acronym Register Description 0x0584 QUEUE1_TXDMA_C P Queue Transmit DMA Completion Pointer Register 1 Section 5.50 0x0588 QUEUE2_TXDMA_C P Queue Transmit DMA Completion Pointer Register 2 Section 5.50 0x058C QUEUE3_TXDMA_C P Queue Transmit DMA Completion Pointer Register 3 Section 5.50 0x0590 QUEUE4_TXDMA_C P Queue Transmit DMA Completion Pointer Register 4 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description 0x0630 QUEUE12_RXDMA_ HDP Queue Receive DMA Head Descriptor Pointer Register 12 Section 5.51 0x0634 QUEUE13_RXDMA_ HDP Queue Receive DMA Head Descriptor Pointer Register 13 Section 5.51 0x0638 QUEUE14_RXDMA_ HDP Queue Receive DMA Head Descriptor Pointer Register 14 Section 5.51 0x063C QUEUE15_RXDMA_ HDP Queue Receive DMA Head Descriptor Pointer Register 15 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) 94 Offset Acronym 0x071C TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 6 SKS6 Register Description Section 5.54 Section 0x0720 TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 7 SKS7 Section 5.54 0x0740 RX_QUEUE_TEAR_ DOWN Receive Queue Teardown Register Section 5.55 0x0744 RX_CPPI_CNTL Receive CPPI Control Register Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description 0x0890 RXU_MAP_L18 MailBox-to-Queue Mapping Register L18 Section 5.61 Section 0x0894 RXU_MAP_H18 MailBox-to-Queue Mapping Register H18 Section 5.62 0x0898 RXU_MAP_L19 MailBox-to-Queue Mapping Register L19 Section 5.61 0x089C RXU_MAP_H19 MailBox-to-Queue Mapping Register H19 Section 5.62 0x08A0 RXU_MAP_L20 MailBox-to-Queue Mapping Register L20 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) 96 Offset Acronym Register Description Section 0x1008 ASBLY_ID Assembly Identity CAR Section 5.66 0x100C ASBLY_INFO Assembly Information CAR Section 5.67 0x1010 PE_FEAT Processing Element Features CAR Section 5.68 0x1018 SRC_OP Source Operations CAR Section 5.69 0x101C DEST_OP Destination Operations CAR Section 5.70 0x104C PE_LL_CTL Processing Element Logical Layer Control CSR Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym 0x2048 SP0_ERR_ATTR_CA Port 0 Attributes Error Capture CSR 0 PT_DBG0 Register Description Section 5.96 Section 0x204C SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 1 G1 Section 5.97 0x2050 SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 2 G2 Section 5.98 0x2054 SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 3 G3 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) 98 Offset Acronym Register Description Section 0x2128 SP3_ERR_RATE Port 3 Error Rate CSR Section 5.101 0x212C SP3_ERR_THRESH Port 3 Error Rate Threshold CSR Section 5.102 0x12000 SP_IP_DISCOVERY _TIMER Port IP Discovery Timer in 4x mode Section 5.103 0x12004 SP_IP_MODE Port IP Mode CSR Section 5.104 0x12008 IP_PRESCAL Serial Port IP Prescalar Section 5.
www.ti.com SRIO Registers 5.2 Peripheral Identification Register (PID) The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. All bits within this register are read-only (writes have no effect) meaning that the values within this register should be hard-coded with the appropriate values and must not change from their reset state. Figure 58.
www.ti.com SRIO Registers 5.3 Peripheral Control Register (PCR) The peripheral control register (PCR) contains a bit that enables or disables the entire peripheral and one bit for every module within the peripheral where this level of control is desired. The module control bits can only be written when the peripheral itself is enabled. In addition, the PCR has emulation control bits free and soft, which control the peripheral behavior during emulation halts. Figure 59.
www.ti.com SRIO Registers 5.4 Peripheral Settings Control Register (PER_SET_CNTL) Figure 60.
www.ti.com SRIO Registers Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit 17-15 Field Value TX_PRI1_WM Description Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send priority 1 packets across the UDI interface. This is valid for all ports in 1X mode only.
www.ti.com SRIO Registers Table 31.
www.ti.com SRIO Registers 5.5 Peripheral Global Enable Register (GBL_EN) Figure 61. Peripheral Global Enable Register (GBL_EN) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-1 0 Reserved EN R-0x00 RW0x00 LEGEND: R = Read only; -n = value after reset Table 32.
www.ti.com SRIO Registers 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) Figure 62. Peripheral Global Enable Status Register (GBL_EN_STAT) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15 1 0 Reserved GBL_ EN_S TAT R-0x00 RUndefi ned LEGEND: R = Read only; -n = value after reset Table 33.
www.ti.com SRIO Registers 5.7 Block n Enable Register (BLKn_EN) There are nine of these registers, one for each of nine logical blocks in the peripheral. Figure 63. Block n Enable Register (BLKn_EN) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-1 0 Reserved EN R-0x00 RWUndefi ned LEGEND: R = Read only; -n = value after reset Table 34.
www.ti.com SRIO Registers 5.8 Block n Enable Status Register (BLKn_EN_STAT) There are nine of these registers, one for each of nine logical blocks in the peripheral. Figure 64. Block n Enable Status Register (BLKn_EN_STAT) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-1 0 Reserved EN_S TAT R-0x00 RUndefi ned LEGEND: R = Read only; -n = value after reset Table 35.
www.ti.com SRIO Registers 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) Figure 65. RapidIO DEVICEID1 Register (DEVICEID_REG1) 31-24 23-16 Reserved 8BNODEID R-0x0000 RW-0x00FF LEGEND: R = Read only; -n = value after reset 15-0 16BNODEID RW-0xFFFF LEGEND: R = Read only; -n = value after reset Table 36.
www.ti.com SRIO Registers 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) Figure 66. RapidIO DEVICEID2 Register (DEVICEID_REG2) 31-24 23-16 Reserved 8BNODEID R-0x0000 RW-0x00FF LEGEND: R = Read only; -n = value after reset 15-0 16BNODEID RW-0xFFFF LEGEND: R = Read only; -n = value after reset Table 37.
www.ti.com SRIO Registers 5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTLn) There are four of these registers, to support four ports. Figure 67. Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTLn) 31-16 16BIT_DEVID_UP_BOUND RW-0xFFFF LEGEND: R = Read only; -n = value after reset 15-0 16BIT_DEVID_LOW_BOUND RW-0xFFFF LEGEND: R = Read only; -n = value after reset Table 38.
www.ti.com SRIO Registers 5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTLn) There are four of these registers, to support four ports. Figure 68. Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTLn) 31-18 17-16 Reserved OUT_BOUND_ PORT R-0x00 RW-0x03 LEGEND: R = Read only; -n = value after reset 15-8 7-0 8BIT_DEVID_UP_BOUND 8BIT_DEVID_LOW_BOUND RW-0xFF RW-0xFF LEGEND: R = Read only; -n = value after reset Table 39.
www.ti.com SRIO Registers 5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL) There are four of these registers, to support four ports. Figure 69.
www.ti.com SRIO Registers Table 40. SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL) Field Descriptions (continued) Bit Field 11 Reserved Reserved. 10:8 TERM Termination. Selects input termination options suitable for a variety of AC or DC coupled scenarios. 7 6:5 4:2 Value 000 Common point connected to VDDT. This configuration is for DC coupled systems using CML transmitters. The common mode voltage is determined jointly by both the receiver and the transmitter.
www.ti.com SRIO Registers 5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTXn_CNTL) There are four of these registers, to support four ports. Figure 70. SERDES Transmit Channel Configuration Registers n (SERDES_CFGTXn_CNTL) 31 17 15 12 11 9 16 Reserved ENFT P R-0 R/W-0 8 7 1 0 DE SWING CM INVPA IR 6 RATE 5 4 BUSWIDTH 2 Reserv ed ENTX R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value at reset Table 42.
www.ti.com SRIO Registers Table 43. SWING Bits CFGTX[11:9] Amplitude (mVdfpp) 000 125 001 250 010 500 011 625 100 750 101 1000 110 1125 111 1250 Table 44. DE Bits CFGTX[15:12] Amplitude Reduction % dB 0000 0 0 0001 4.76 -0.42 0010 9.52 -0.87 0011 14.28 -1.34 0100 19.04 -1.83 0101 23.8 -2.36 0110 28.56 -2.92 0111 33.32 -3.52 1000 38.08 -4.16 1001 42.85 -4.86 1010 47.61 -5.61 1011 52.38 -6.44 1100 57.14 -7.35 1101 61.9 -8.38 1110 66.66 -9.
www.ti.com SRIO Registers 5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) There are four of these registers, to support four ports. Figure 71. SERDES Macros CFG (0-3) Registers (SERDES_CFGn_CNTL) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LB Reserved MPY ENPLL R-0 R/W-0 R-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value at reset Table 45.
www.ti.com SRIO Registers 5.16 DOORBELLn Interrupt Status Register (DOORBELLn_ICSR) Each of the four doorbells is supported by a register of this type. Figure 72. DOORBELLn Interrupt Status Register (DOORBELLn_ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; -n = value after reset Table 46.
www.ti.com SRIO Registers 5.17 DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR) Each of the four doorbells is supported by a register of this type. Figure 73. DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; -n = value after reset Table 47.
www.ti.com SRIO Registers 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Figure 74. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; -n = value after reset Table 48.
www.ti.com SRIO Registers 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Figure 75. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; -n = value after reset Table 49.
www.ti.com SRIO Registers 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Figure 76. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; -n = value after reset Table 50.
www.ti.com SRIO Registers 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Figure 77. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; -n = value after reset Table 51.
www.ti.com SRIO Registers 5.22 LSU Status Interrupt Register (LSU_ICSR) Figure 78. LSU Status Interrupt Register (LSU_ICSR) 31-16 ICS(31-16) R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICS(15-0) R-0x00 LEGEND: R = Read only; -n = value after reset Table 52.
www.ti.com SRIO Registers 5.23 LSU Clear Interrupt Register (LSU _ICCR) Figure 79. LSU Clear Interrupt Register (LSU _ICCR) 31-16 ICC(31-16) W-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ICC(15-0) W-0x00 LEGEND: R = Read only; -n = value after reset Table 53.
www.ti.com SRIO Registers 5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) Figure 80.
www.ti.com SRIO Registers 5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) Figure 81. Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) 31-17 16 Reserved ICC16 R-0x00 W0x00 LEGEND: R = Read only; -n = value after reset 15-12 11 10 9 8 7-3 2 1 0 Reserved ICC11 ICC10 ICC9 ICC8 Reserved ICC2 ICC1 ICC0 R-0x00 W0x00 W0x00 W0x00 W0x00 R-0x00 W0x00 W0x00 W0x00 LEGEND: R = Read only; -n = value after reset Table 55.
www.ti.com SRIO Registers 5.26 DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) Each of the four doorbells is supported by a register of this type. Figure 82. DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 56.
www.ti.com SRIO Registers 5.27 DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) Each of the four doorbells is supported by a register of this type. Figure 83. DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 57.
www.ti.com SRIO Registers 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Figure 84. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 58.
www.ti.com SRIO Registers 5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) Figure 85.
www.ti.com SRIO Registers 5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Figure 86. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 60.
www.ti.com SRIO Registers 5.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Figure 87. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R/W-0x00 R/W-0x00 R/W-0x00 R/W-0x00 LEGEND: R = Read, W = Write, n = value at reset Table 61.
www.ti.com SRIO Registers 5.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Figure 88. LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 62.
www.ti.com SRIO Registers 5.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Figure 89. LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) 31 28 27 24 23 20 19 16 ICR15 ICR14 ICR13 ICR12 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 63.
www.ti.com SRIO Registers 5.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Figure 90. LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) 31 28 27 24 23 20 19 16 ICR23 ICR22 ICR21 ICR20 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR19 ICR18 ICR17 ICR16 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 64.
www.ti.com SRIO Registers 5.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Figure 91. LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) 31 28 27 24 23 20 19 16 ICR31 ICR30 ICR29 ICR28 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR27 ICR26 ICR25 ICR24 R/W-0000 R/W-0000 R/W-0000 R/W-0000 LEGEND: R = Read, W = Write, n = value at reset Table 65.
www.ti.com SRIO Registers 5.36 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) Figure 92. Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-12 11-8 7-4 3-0 Reserved ICR2 ICR1 ICR0 R-0x00 RW-0x00 RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 66.
www.ti.com SRIO Registers 5.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) Figure 93. Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-12 11-8 7-4 3-0 ICR11 ICR10 ICR9 ICR8 RW-0x00 RW-0x00 RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 67.
www.ti.com SRIO Registers 5.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) Figure 94. Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-4 3-0 Reserved ICR16 R-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 68.
www.ti.com SRIO Registers 5.39 INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE) There are eight of these registers. Figure 95. INTDSTn Interrupt Status Decode Registers (INTDSTn_DECODE) 31-16 ISDR[31-16] R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ISDR[15-0] R-0x00 LEGEND: R = Read only; -n = value after reset Table 69.
www.ti.com SRIO Registers 5.40 INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL) There are eight of these registers. Figure 96. INTDSTn Interrupt Rate Control Registers (INTDSTn_RATE_CNTL) 31-16 COUNT_DOWN_VALUE RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 COUNT_DOWN_VALUE RW-0x00 LEGEND: R = Read only; -n = value after reset Table 70.
www.ti.com SRIO Registers 5.41 LSUn Control Register 0 (LSUn_REG0) There are four of these registers, one for each LSU. Figure 97. LSUn Control Register 0 (LSUn_REG0) 31-16 ADDRESS_MSB RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ADDRESS_MSB RW-0x00 LEGEND: R = Read only; -n = value after reset Table 71.
www.ti.com SRIO Registers 5.42 LSUn Control Register 1 (LSUn_REG1) There are four of these registers, one for each LSU. Figure 98. LSUn Control Register 1 (LSUn_REG1) 31-16 ADDRESS_LSB_CONFIG_OFFSET RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ADDRESS_LSB_CONFIG_OFFSET RW-0x00 LEGEND: R = Read only; -n = value after reset Table 72.
www.ti.com SRIO Registers 5.43 LSUn Control Register 2 (LSUn_REG2) There are four of these registers, one for each LSU. Figure 99. LSUn Control Register 2 (LSUn_REG2) 31-16 DSP_ADDRESS RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 DSP_ADDRESS RW-0x00 LEGEND: R = Read only; -n = value after reset Table 73.
www.ti.com SRIO Registers 5.44 LSUn Control Register 3 (LSUn_REG3) There are four of these registers, one for each LSU. Figure 100. LSUn Control Register 3 (LSUn_REG3) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-12 11-0 Reserved BYTE_COUNT R-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 74.
www.ti.com SRIO Registers 5.45 LSUn Control Register 4 (LSUn_REG4) There are four of these registers, one for each LSU. Figure 101. LSUn Control Register 4 (LSUn_REG4) 31-30 29-28 27-26 25-24 23-16 OUTPORTID PRIORITY XAMBS ID_SIZE DESTID RW-0x00 RW-0x00 RW-0x00 RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset 15-8 7-1 0 DESTID Reserved INTER RUPT _REQ RW-0x00 R-0x00 RW0x00 LEGEND: R = Read only; -n = value after reset Table 75.
www.ti.com SRIO Registers 5.46 LSUn Control Register 5 (LSUn_REG5) There are four of these registers, one for each LSU. Figure 102. LSUn Control Register 5 (LSUn_REG5) 31-16 DRBLL_INFO RW-0x00 LEGEND: R = Read only; -n = value after reset 15-8 7-0 HOP_COUNT PACKET_TYPE RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 76.
www.ti.com SRIO Registers 5.47 LSUn Control Register 6 (LSUn_REG6) There are four of these registers, one for each LSU. Figure 103. LSUn Control Register 6 (LSUn_REG6) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-5 4-1 0 Reserved COMPLETION_CODE BSY R-0x00 R-0x00 R0x00 LEGEND: R = Read only; -n = value after reset Table 77.
www.ti.com SRIO Registers 5.48 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) Figure 104. LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 FLOW_MASK (0-15) RW-0x01 LEGEND: R = Read only; -n = value after reset Table 78.
www.ti.com SRIO Registers 5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) There are sixteen of these registers. Figure 105. Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) 31-16 TX_HDP RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 TX_HDP RW-0x00 LEGEND: R = Read only; -n = value after reset Table 79.
www.ti.com SRIO Registers 5.50 Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) There are sixteen of these registers. Figure 106. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) 31-16 TX_CP RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 TX_CP RW-0x00 LEGEND: R = Read only; -n = value after reset Table 80.
www.ti.com SRIO Registers 5.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) There are sixteen of these registers. Figure 107. Queue Receive DMA Head Descriptor Pointer Registers (QUEUEn_RXDMA_HDP) 31-16 RX_HDP RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 RX_HDP RW-0x00 LEGEND: R = Read only; -n = value after reset Table 81.
www.ti.com SRIO Registers 5.52 Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP) There are sixteen of these registers. Figure 108. Queue Receive DMA Completion Pointer Registers (QUEUEn_RXDMA_CP) 31-16 RX_CP RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 RX_CP RW-0x00 LEGEND: R = Read only; -n = value after reset Table 82.
www.ti.com SRIO Registers 5.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Figure 109.
www.ti.com SRIO Registers 5.54 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKSn) There are eight registers of this type. See Figure 28 for more information on this register. Figure 110.
www.ti.com SRIO Registers Transmit CPPI Supported Flow Mask Register 7 (TX_CPPI_FLOW_MASKS7) 31-16 15-0 QUEUE15_FLOW_MASK QUEUE14_FLOW_MASK RW-0x01 RW-0x01 LEGEND: R = Read only; -n = value after reset Table 84.
www.ti.com SRIO Registers 5.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Figure 111.
www.ti.com SRIO Registers 5.56 Receive CPPI Control Register (RX_CPPI_CNTL) Figure 112.
www.ti.com SRIO Registers 5.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) Figure 113.
www.ti.com SRIO Registers 5.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) Figure 114.
www.ti.com SRIO Registers 5.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) Figure 115.
www.ti.com SRIO Registers 5.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) Figure 116.
www.ti.com SRIO Registers 5.61 Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln) Figure 117. Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln) 31-30 29-24 23-22 21-16 LETTER_MAS K MAILBOX_MASK LETTER MAILBOX RW-0x03 RW-0x3F RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 SOURCEID RW-0x00 LEGEND: R = Read only; -n = value after reset Table 91.
www.ti.com SRIO Registers 5.62 Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Figure 118. Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-10 9-8 7-6 5-2 Reserved TT Reserved QUEUE_ID 1 R-0x00 RW-0x01 R-0x00 RW-0x00 0 PROM SEGM ISCUO ENT_ US MAPPI NG RW0x00 RW0x00 LEGEND: R = Read only; -n = value after reset Table 92.
www.ti.com SRIO Registers 5.63 Flow Control Table Entry Registers (FLOW_CNTLn) There are sixteen of these registers. Figure 119. Flow Control Table Entry Registers (FLOW_CNTLn) 31-18 17-16 Reserved TT R-0x00 RW-0x01 LEGEND: R = Read only; -n = value after reset 15-0 FLOW_CNTL_ID RW-0x00 LEGEND: R = Read only; -n = value after reset Table 93.
www.ti.com SRIO Registers 5.64 Device Identity CAR (DEV_ID) Figure 120. Device Identity CAR (DEV_ID) 31-16 DEVICEIDENTITY R-0x0000 LEGEND: R = Read only; -n = value after reset 15-0 DEVICE_VENDORIDENTITY R-0x0030 LEGEND: R = Read only; -n = value after reset Table 94. Device Identity CAR (DEV_ID) Field Descriptions Bit Field Value Description 31-16 DEVICEIDENTIT Y Identifies the type of device. Vendor specific.
www.ti.com SRIO Registers 5.65 Device Information CAR (DEV_INFO) Figure 121. Device Information CAR (DEV_INFO) 31-16 DEVICEREV R-0x0000 LEGEND: R = Read only; -n = value after reset 15-0 DEVICEREV R-0x0000 LEGEND: R = Read only; -n = value after reset Table 95.
www.ti.com SRIO Registers 5.66 Assembly Identity CAR (ASBLY_ID) Figure 122. Assembly Identity CAR (ASBLY_ID) 31-16 ASSY_IDENTITY R-0x0000 LEGEND: R = Read only; -n = value after reset 15-0 ASSY_VENDORIDENTITY R-0x0030 LEGEND: R = Read only; -n = value after reset Table 96. Assembly Identity CAR (ASBLY_ID) Field Descriptions Bit Field Value Description 31-16 ASSY_IDENTITY Assembly Identifier. Vendor Specific. 15-0 ASSY_VENDORI DENTITY Assembly Vendor Identifier assigned by RapidIO TA.
www.ti.com SRIO Registers 5.67 Assembly Information CAR (ASBLY_INFO) Figure 123. Assembly Information CAR (ASBLY_INFO) 31-16 ASSYREV R-0x0000 LEGEND: R = Read only; -n = value after reset 15-0 EXTENDEDFEATURESPTR R-0x0100 LEGEND: R = Read only; -n = value after reset Table 97.
www.ti.com SRIO Registers 5.68 Processing Element Features CAR (PE_FEAT) Figure 124.
www.ti.com SRIO Registers 5.69 Source Operations CAR (SRC_OP) Figure 125.
www.ti.com SRIO Registers 5.70 Destination Operations CAR (DEST_OP) Figure 126.
www.ti.com SRIO Registers 5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL) Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL) 31-16 Reserved R-0x0000 LEGEND: R = Read only; -n = value after reset 15-3 2-0 Reserved EXTENDED_ADDRESS ING_CONTROL R-0x0000 RW-0x0001 LEGEND: R = Read only; -n = value after reset Table 101.
www.ti.com SRIO Registers 5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Figure 128. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) 31 30-16 Reserv ed LCSBA R0x00 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 LCSBA R-0x00 LEGEND: R = Read only; -n = value after reset Table 102.
www.ti.com SRIO Registers 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Figure 129. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) 31-16 LCSBA R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 LCSBA R-0x00 LEGEND: R = Read only; -n = value after reset Table 103.
www.ti.com SRIO Registers 5.74 Base Device ID CSR (BASE_ID) Figure 130. Base Device ID CSR (BASE_ID) 31-24 23-16 Reserved BASE_DEVICEID R-0x00 RW-0x00FF LEGEND: R = Read only; -n = value after reset 15-0 LARGE_BASE_DEVICEID RW-0xFFFF LEGEND: R = Read only; -n = value after reset Table 104.
www.ti.com SRIO Registers 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) See Section 2.4.2 of the RapidIO Specification for description of this register. It provides a lock function that is write-once/reset-able. Figure 131. Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 HOST_BASE_DEVICEID RW-0xFFFF LEGEND: R = Read only; -n = value after reset Table 105.
www.ti.com SRIO Registers 5.76 Component Tag CSR (COMP_TAG) Figure 132. Component Tag CSR (COMP_TAG) 31-16 COMPONENT_TAG RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 COMPONENT_TAG RW-0x00 LEGEND: R = Read only; -n = value after reset Table 106. Component Tag CSR (COMP_TAG) Field Descriptions Bit 31-0 178 Field COMPONENT_T AG Serial RapidIO (SRIO) Value Description Software defined component Tag for PE. Useful for devices without device IDs.
www.ti.com SRIO Registers 5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Figure 133. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) 31-16 EF_PTR R-0x1000 LEGEND: R = Read only; -n = value after reset 15-0 EF_ID R-0x0001 LEGEND: R = Read only; -n = value after reset Table 107.
www.ti.com SRIO Registers 5.78 Port Link Time-Out Control CSR (SP_LT_CTL) Figure 134. Port Link Time-Out Control CSR (SP_LT_CTL) 31-16 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; -n = value after reset 15-8 7-0 TIMEOUT_VALUE Reserved RW-0xFFFFFF R-0x00 LEGEND: R = Read only; -n = value after reset Table 108. Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions Bit 31-8 Field TIMEOUT_VALU E Value Description Timeout value for all ports on the device.
www.ti.com SRIO Registers 5.79 Port Response Time-Out Control CSR (SP_RT_CTL) Figure 135. Port Response Time-Out Control CSR (SP_RT_CTL) 31-16 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; -n = value after reset 15-8 7-0 TIMEOUT_VALUE Reserved RW-0xFFFFFF R-0x00 LEGEND: R = Read only; -n = value after reset Table 109. Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions Bit Field Value Description 31-8 TIMEOUT_VALU E Timeout value for all ports on the device.
www.ti.com SRIO Registers 5.80 Port General Control CSR (SP_GEN_CTL) Figure 136. Port General Control CSR (SP_GEN_CTL) 31 HOST RW0x00 30 29 28-16 MAST DISCO ER_E VERE NABL D E RW0x00 Reserved RW0x00 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 110.
www.ti.com SRIO Registers 5.81 Port Link Maintenance Request CSR n (SPn_LM_REQ) Each of the four ports is supported by a register of this type. Figure 137. Port Link Maintenance Request CSR n (SPn_LM_REQ) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-3 2-0 Reserved COMMAND R-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 111.
www.ti.com SRIO Registers 5.82 Port Link Maintenance Response CSR n (SPn_LM_RESP) Each of the four ports is supported by a register of this type. Figure 138. Port Link Maintenance Response CSR n (SPn_LM_RESP) 31 30-16 RESP ONSE _VALI D Reserved R0x00 R-0x00 LEGEND: R = Read only; -n = value after reset 15-10 9-5 4-0 Reserved ACKID_STATUS LINK_STATUS R-0x00 R-0x00 R-0x00 LEGEND: R = Read only; -n = value after reset Table 112.
www.ti.com SRIO Registers 5.83 Port Local AckID Status CSR n (SPn_ACKID_STAT) Each of the four ports is supported by a register of this type. Figure 139. Port Local AckID Status CSR n (SPn_ACKID_STAT) 31-29 28-24 23-16 Reserved INBOUND_ACKID Reserved R-0x00 RW-0x00 R-0x00 LEGEND: R = Read only; -n = value after reset 15-13 12-8 7-5 4-0 Reserved OUTSTANDING_ACKID Reserved OUTBOUND_ACKID R-0x00 RW-0x00 R-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 113.
www.ti.com SRIO Registers 5.84 Port Error and Status CSR n (SPn_ERR_STAT) Each of the four ports is supported by a register of this type. Figure 140.
www.ti.com SRIO Registers Table 114. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued) Bit Field Value Description 1 PORT_OK The input and output ports are initialized and the port is exchanging error-free control symbols with the attached device (read-only). 0 PORT_UNINITIA LIZED Input and output ports are not initialized. This bit and bit 1 are mutually exclusive (read-only).
www.ti.com SRIO Registers 5.85 Port Control CSR n (SPn_CTL) Each of the four ports is supported by a register of this type. Figure 141.
www.ti.com SRIO Registers Table 115. Port Control CSR n (SPn_CTL) Field Descriptions (continued) Bit Field 21 INPUT_PORT_E NABLE 20 Value Description Input port receive enable 0b Port is stopped and only enabled to route or respond I/O logical MAINTENANCE packets, depending upon the functionality of the processing element. Other packets generate packet-not-accepted control symbols to force an error condition to be signaled by the sending device.
www.ti.com SRIO Registers 5.86 Error Reporting Block Header (ERR_RPT_BH) Figure 142. Error Reporting Block Header (ERR_RPT_BH) 31-16 EF_PTR R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 EF_ID R-0x0007 LEGEND: R = Read only; -n = value after reset Table 116. Error Reporting Block Header (ERR_RPT_BH) Field Descriptions Bit Field Value Description 31-16 EF_PTR Hard wired pointer to the next block in the data structure.
www.ti.com SRIO Registers 5.87 Logical/Transport Layer Error Detect CSR (ERR_DET) Figure 143.
www.ti.com SRIO Registers 5.88 Logical/Transport Layer Error Enable CSR (ERR_EN) Figure 144.
www.ti.com SRIO Registers 5.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Figure 145. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) 31-16 ADDRESS_63_32 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 ADDRESS_63_32 R-0x00 LEGEND: R = Read only; -n = value after reset Table 119.
www.ti.com SRIO Registers 5.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Figure 146. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) 31-16 ADDRESS_31_3 R-0x00 LEGEND: R = Read only; -n = value after reset 15-3 2 1-0 ADDRESS_31_3 Reserv ed XAMSBS R-0x00 R0x00 R-0x00 LEGEND: R = Read only; -n = value after reset Table 120.
www.ti.com SRIO Registers 5.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Figure 147. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) 31-24 23-16 MSB_DESTID DESTID R-0x00 R-0x00 LEGEND: R = Read only; -n = value after reset 15-8 7-0 MSB_SOURCEID SOURCEID R-0x00 R-0x00 LEGEND: R = Read only; -n = value after reset Table 121.
www.ti.com SRIO Registers 5.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Figure 148. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) 31-28 27-24 23-16 FTYPE TTYPE MSGINFO R-0x00 R-0x00 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 IMP_SPECIFIC R-0x00 LEGEND: R = Read only; -n = value after reset Table 122.
www.ti.com SRIO Registers 5.93 Port-Write Target Device ID CSR (PW_TGT_ID) Figure 149. Port-Write Target Device ID CSR (PW_TGT_ID) 31-24 23-16 DEVICEID_MSB DEVICEID RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 123.
www.ti.com SRIO Registers 5.94 Port Error Detect CSR n (SPn_ERR_DET) Each of the four ports is supported by a register of this type. Figure 150.
www.ti.com SRIO Registers 5.95 Port Error Rate Enable CSR n (SPn_RATE_EN) Each of the four ports is supported by a register of this type. Figure 151.
www.ti.com SRIO Registers 5.96 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) Each of the four ports is supported by a register of this type. Figure 152.
www.ti.com SRIO Registers 5.97 Port n Packet/Control Symbol Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) Each of the four ports is supported by a register of this type. Figure 153. Port n Packet/Control Symbol Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) 31-16 CAPTURE0 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 CAPTURE0 R-0x00 LEGEND: R = Read only; -n = value after reset Table 127.
www.ti.com SRIO Registers 5.98 Port n Packet/Control Symbol Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) Each of the four ports is supported by a register of this type. Figure 154. Port n Packet/Control Symbol Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) 31-16 CAPTURE1 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 CAPTURE1 R-0x00 LEGEND: R = Read only; -n = value after reset Table 128.
www.ti.com SRIO Registers 5.99 Port n Packet/Control Symbol Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) Each of the four ports is supported by a register of this type. Figure 155. Port n Packet/Control Symbol Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) 31-16 CAPTURE2 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 CAPTURE2 R-0x00 LEGEND: R = Read only; -n = value after reset Table 129.
www.ti.com SRIO Registers 5.100 Port n Packet/Control Symbol Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) Each of the four ports is supported by a register of this type. Figure 156. Port n Packet/Control Symbol Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) 31-16 CAPTURE3 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 CAPTURE3 R-0x00 LEGEND: R = Read only; -n = value after reset Table 130.
www.ti.com SRIO Registers 5.101 Port Error Rate CSR n (SPn_ERR_RATE) Each of the four ports is supported by a register of this type. Figure 157. Port Error Rate CSR n (SPn_ERR_RATE) 31-24 23-18 17-16 ERROR_RATE_BIAS Reserved ERROR_RATE _RECOVERY RW-0xFF R-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset 15-8 7-0 PEAK_ERROR_RATE ERROR_RATE_COUNTER RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset Table 131.
www.ti.com SRIO Registers 5.102 Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Each of the four ports is supported by a register of this type. Figure 158. Port Error Rate Threshold CSR n (SPn_ERR_THRESH) 31-24 23-16 ERROR_RATE_FAILED_THRESHOLD ERROR_RATE_DEGRADED_THRES RW-0xFF RW-0xFF LEGEND: R = Read only; -n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 132.
www.ti.com SRIO Registers 5.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) Figure 159. Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) 31-28 27-24 23-20 19-16 DISCOVERY_TIMER Reserved PW_TIMER Reserved RW-0x09 R-0x00 RW-0x08 R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 133.
www.ti.com SRIO Registers 5.104 Port IP Mode CSR (SP_IP_MODE) Figure 160.
www.ti.com SRIO Registers Table 134. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued) Bit 3 Field Value RST_EN Description Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are received in a sequence 0b Reset interrupt disable 1b Reset interrupt enable 2 RST_CS Reset received status bit. It is set when 4 reset control symbols are received in a sequence. Once set, it remains set until written with logic 1 to clear.
www.ti.com SRIO Registers 5.105 Serial Port IP Prescalar (IP_PRESCAL) Figure 161. Serial Port IP Prescalar (IP_PRESCAL) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-8 7-0 Reserved PRESCALE R-0x00 RW-0x0F LEGEND: R = Read only; -n = value after reset Table 135. Serial Port IP Prescalar (IP_PRESCAL) Field Descriptions Bit Field Value Description 31-8 Reserved Reserved 7-0 PRESCALE For different frequencies of the DMA clock, use the formula: [DMA freq * 16/156.
www.ti.com SRIO Registers 5.106 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPTn) Each of the four ports is supported by a register of this type. Figure 162. Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPTn) 31-16 PW_CAPTn R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 PW_CAPTn R-0x00 LEGEND: R = Read only; -n = value after reset Table 136.
www.ti.com SRIO Registers 5.107 Port Reset Option CSR n (SPn_RST_OPT) Each of the four ports is supported by a register of this type. Figure 163. Port Reset Option CSR n (SPn_RST_OPT) 31-16 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset 15-8 7-0 Reserved PORT_ID R-0x00 R-Undefined LEGEND: R = Read only; -n = value after reset Table 137.
www.ti.com SRIO Registers 5.108 Port Control Independent Register n (SPn_CTL_INDEP) Each of the four ports is supported by a register of this type. Figure 164.
www.ti.com SRIO Registers Table 138. Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions (continued) Bit Field 17 MAX_RETRY_EN Value Description Max_retry_error report enable. If enabled, the Port-Write and interrupt are reported as errors. 1b Max retry error report enable 0b Max retry error report disable 16 MAX_RETRY_ER R Max_retry_error bit is set when max_retry_cnt is equal to max_retry_threshold. The Port-Write request and interrupt are generated if enabled.
www.ti.com SRIO Registers 5.109 Port Silence Timer n (SPn_SILENCE_TIMER) Each of the four ports is supported by a register of this type. Figure 165. Port Silence Timer n (SPn_SILENCE_TIMER) 31-28 27-16 SILENCE_TIMER Reserved RW-0x0B R-0x00 LEGEND: R = Read only; -n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; -n = value after reset Table 139. Port Silence Timer n (SPn_SILENCE_TIMER) Field Descriptions Bit 31-28 Field Value SILENCE_TIMER Description Silence timer.
www.ti.com SRIO Registers 5.110 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Each of the four ports is supported by a register of this type. Figure 166. Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) 31-16 MULT_EVNT_CS W-0x00 LEGEND: R = Read only; -n = value after reset 15-0 MULT_EVNT_CS W-0x00 LEGEND: R = Read only; -n = value after reset Table 140.
www.ti.com SRIO Registers 5.111 Port Control Symbol Transmit n (SPn_CS_TX) Each of the four ports is supported by a register of this type. Figure 167. Port Control Symbol Transmit n (SPn_CS_TX) 31-29 28-24 23-19 18-16 STYPE_0 PAR_0 PAR_1 STYPE_1 RW-0x00 RW-0x00 RW-0x00 RW-0x00 LEGEND: R = Read only; -n = value after reset 15-13 12 11-0 CMD CS_E MB Reserved RW-0x00 RW0x00 R-0x00 LEGEND: R = Read only; -n = value after reset Table 141.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
