Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide

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5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH)
Ethernet Media Access Controller (EMAC) Registers
The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 66
and described in Table 65 .
Figure 66. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
31 16
Reserved
R-0
15 8 7 0
Reserved RXFILTERTHRESH
R-0 R/W-0
LEGEND: R = Read only; R/W = Read/Write; - n = value after reset
Table 65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 RXFILTERTHRESH 0-FFh Receive filter low threshold. These bits contain the free buffer count threshold value for filtering
low priority incoming frames. This field should remain 0, if no filtering is desired.
The receive channel 0-7 flow control threshold register (RX nFLOWTHRESH) is shown in Figure 67 and
described in Table 66 .
Figure 67. Receive Channel n Flow Control Threshold Register (RX nFLOWTHRESH)
31 16
Reserved
R-0
15 8 7 0
Reserved RX nFLOWTHRESH
R-0 R/W-0
LEGEND: R = Read only; R/W = Read/Write; - n = value after reset
Table 66. Receive Channel n Flow Control Threshold Register (RX nFLOWTHRESH)
Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 RX nFLOWTHRESH 0-FFh Receive flow threshold. These bits contain the threshold value for issuing flow control on
incoming frames for channel n (when enabled).
108 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUEQ6 – December 2007
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