Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide

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5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX nHDP)
5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RX nHDP)
Ethernet Media Access Controller (EMAC) Registers
The transmit channel 0-7 DMA head descriptor pointer register (TX nHDP) is shown in Figure 86 and
described in Table 85 .
Figure 86. Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP)
31 16
TX nHDP
R/W-x
15 0
TX nHDP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset; -x = value is indeterminate after reset
Table 85. Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP)
Field Descriptions
Bit Field Value Description
31-0 TX nHDP 0-FFFF FFFFh Transmit channel n DMA Head Descriptor pointer. Writing a transmit DMA buffer descriptor
address to a head pointer location initiates transmit DMA operations in the queue for the
selected channel. Writing to these locations when they are nonzero is an error (except at reset).
Host software must initialize these locations to 0 on reset.
The receive channel 0-7 DMA head descriptor pointer register (RX nHDP) is shown in Figure 87 and
described in Table 86 .
Figure 87. Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP)
31 16
RX nHDP
R/W-x
15 0
RX nHDP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset; -x = value is indeterminate after reset
Table 86. Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP)
Field Descriptions
Bit Field Value Description
31-0 RX nHDP 0-FFFF FFFFh Receive channel n DMA Head Descriptor pointer. Writing a receive DMA buffer descriptor
address to this location allows receive DMA operations in the selected channel when a channel
frame is received. Writing to these locations when they are nonzero is an error (except at reset).
Host software must initialize these locations to 0 on reset.
122 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUEQ6 – December 2007
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