Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide

4.3 PHY Acknowledge Status Register (ALIVE) ................................................................ 73
4.4 PHY Link Status Register (LINK) ............................................................................. 73
4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 74
4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .......................... 75
4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ................... 76
4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................. 77
4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ................ 78
4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .......... 79
4.11 MDIO User Access Register 0 (USERACCESS0) ......................................................... 80
4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) .................................................... 81
4.13 MDIO User Access Register 1 (USERACCESS1) ......................................................... 82
4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 83
5 Ethernet Media Access Controller (EMAC) Registers ..................................................... 84
5.1 Transmit Identification and Version Register (TXIDVER) ................................................. 87
5.2 Transmit Control Register (TXCONTROL) .................................................................. 87
5.3 Transmit Teardown Register (TXTEARDOWN) ............................................................ 88
5.4 Receive Identification and Version Register (RXIDVER) .................................................. 89
5.5 Receive Control Register (RXCONTROL) .................................................................. 89
5.6 Receive Teardown Register (RXTEARDOWN) ............................................................. 90
5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .................................... 91
5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................... 92
5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ................................................ 93
5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .......................................... 94
5.11 MAC Input Vector Register (MACINVECTOR) ............................................................. 95
5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) .............................................. 95
5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ..................................... 96
5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................... 97
5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ................................................. 98
5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ........................................... 99
5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ..................................... 100
5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ................................... 100
5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ................................................. 101
5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ........................................... 101
5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .......... 102
5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................... 105
5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) .................................................. 106
5.24 Receive Maximum Length Register (RXMAXLEN) ....................................................... 107
5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) .................................................. 107
5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .................. 108
5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) ....................... 108
5.28 Receive Channel 0-7 Free Buffer Count Register (RX nFREEBUFFER) .............................. 109
5.29 MAC Control Register (MACCONTROL) .................................................................. 110
5.30 MAC Status Register (MACSTATUS) ...................................................................... 112
5.31 Emulation Control Register (EMCONTROL) .............................................................. 114
5.32 FIFO Control Register (FIFOCONTROL) .................................................................. 114
5.33 MAC Configuration Register (MACCONFIG) .............................................................. 115
5.34 Soft Reset Register (SOFTRESET) ........................................................................ 115
5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ....................................... 116
4 Contents SPRUEQ6 – December 2007
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