Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide

5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 116
5.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 117
5.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 117
5.39 Back Off Test Register (BOFFTEST) ....................................................................... 118
5.40 Transmit Pacing Algorithm Test Register (TPACETEST) ............................................... 118
5.41 Receive Pause Timer Register (RXPAUSE) .............................................................. 119
5.42 Transmit Pause Timer Register (TXPAUSE) .............................................................. 119
5.43 MAC Address Low Bytes Register (MACADDRLO) ...................................................... 120
5.44 MAC Address High Bytes Register (MACADDRHI) ...................................................... 121
5.45 MAC Index Register (MACINDEX) ......................................................................... 121
5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX nHDP) ............................ 122
5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RX nHDP) ............................ 122
5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) ........................................... 123
5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) ........................................... 123
5.50 Network Statistics Registers ................................................................................. 124
Appendix A Glossary ...................................................................................................... 133
SPRUEQ6 – December 2007 Contents 5
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