Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide

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3.5 EMAC Control Module Receive Threshold Interrupt Enable Register
3.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
EMAC Control Module Registers
(CMRXTHRESHINTEN)
The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 17 and
described in Table 14 .
Figure 17. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN)
31 16
Reserved
R-0
15 8 7 0
Reserved RXTHRESHEN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 14. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 RXTHRESHEN[ n] Receive threshold interrupt (RXTHRESHPEND n) enable. Each bit controls the corresponding
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt (RXTHRESHPEND n) is disabled.
Bit n = 1, channel n receive threshold interrupt (RXTHRESHPEND n) is enabled.
The receive interrupt enable register (CMRXINTEN) is shown in Figure 18 and described in Table 15 .
Figure 18. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
31 16
Reserved
R-0
15 8 7 0
Reserved RXPULSEEN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 15. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 RXPULSEEN[ n] Receive interrupt (RXPEND n) enable. Each bit controls the corresponding channel n receive
interrupt.
Bit n = 0, channel n receive interrupt (RXPEND n) is disabled.
Bit n = 1, channel n receive interrupt (RXPEND n) is enabled.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)64 SPRUEQ6 – December 2007
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